1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * Copyright (c) 2009 The University of Edinburgh
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are
10 * met: redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer;
12 * redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution;
15 * neither the name of the copyright holders nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Authors: Nathan Binkert
32 * Steve Reinhardt
33 * Stephen Hines
34 * Timothy M. Jones
35 */
36
37#ifndef __ARCH_POWER_TLB_HH__
38#define __ARCH_POWER_TLB_HH__
39
40#include <map>
41
42#include "arch/generic/tlb.hh"
43#include "arch/power/isa_traits.hh"
44#include "arch/power/pagetable.hh"
45#include "arch/power/utility.hh"
46#include "arch/power/vtophys.hh"
47#include "base/statistics.hh"
48#include "mem/request.hh"
49#include "params/PowerTLB.hh"
50
51class ThreadContext;
52
53namespace PowerISA {
54
55// This is copied from the ARM ISA and has not been checked against the
56// Power at all.
57struct TlbEntry
58{
59 Addr _pageStart;
60
61 TlbEntry()
62 {
63 }
64
65 TlbEntry(Addr asn, Addr vaddr, Addr paddr,
66 bool uncacheable, bool read_only)
67 : _pageStart(paddr)
68 {
69 if (uncacheable || read_only)
70 warn("Power TlbEntry does not support uncacheable"
71 " or read-only mappings\n");
72 }
73
74 void
75 updateVaddr(Addr new_vaddr)
76 {
77 panic("unimplemented");
78 }
79
80 Addr
81 pageStart()
82 {
83 return _pageStart;
84 }
85
86 void
87 serialize(CheckpointOut &cp) const
88 {
89 SERIALIZE_SCALAR(_pageStart);
90 }
91
92 void
93 unserialize(CheckpointIn &cp)
94 {
95 UNSERIALIZE_SCALAR(_pageStart);
96 }
97};
98
99class TLB : public BaseTLB
100{
101 protected:
102 typedef std::multimap<Addr, int> PageTable;
103 PageTable lookupTable; // Quick lookup into page table
104
105 PowerISA::PTE *table; // the Page Table
106 int size; // TLB Size
107 int nlu; // not last used entry (for replacement)
108
109 void
110 nextnlu()
111 {
112 if (++nlu >= size) {
113 nlu = 0;
114 }
115 }
116
117 PowerISA::PTE *lookup(Addr vpn, uint8_t asn) const;
118
119 mutable Stats::Scalar read_hits;
120 mutable Stats::Scalar read_misses;
121 mutable Stats::Scalar read_acv;
122 mutable Stats::Scalar read_accesses;
123 mutable Stats::Scalar write_hits;
124 mutable Stats::Scalar write_misses;
125 mutable Stats::Scalar write_acv;
126 mutable Stats::Scalar write_accesses;
127 Stats::Formula hits;
128 Stats::Formula misses;
129 Stats::Formula accesses;
130
131 public:
132 typedef PowerTLBParams Params;
133 TLB(const Params *p);
134 virtual ~TLB();
135
136 void takeOverFrom(BaseTLB *otlb) override {}
137
138 int probeEntry(Addr vpn,uint8_t) const;
139 PowerISA::PTE *getEntry(unsigned) const;
140
141 int smallPages;
142
143 int
144 getsize() const
145 {
146 return size;
147 }
148
149 PowerISA::PTE &index(bool advance = true);
150 void insert(Addr vaddr, PowerISA::PTE &pte);
151 void insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages);
152 void flushAll() override;
153
154 void
155 demapPage(Addr vaddr, uint64_t asn) override
156 {
157 panic("demapPage unimplemented.\n");
158 }
159
160 // static helper functions... really
161 static bool validVirtualAddress(Addr vaddr);
162 static Fault checkCacheability(RequestPtr &req);
163 Fault translateInst(RequestPtr req, ThreadContext *tc);
164 Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
| 1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * Copyright (c) 2009 The University of Edinburgh
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are
10 * met: redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer;
12 * redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution;
15 * neither the name of the copyright holders nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Authors: Nathan Binkert
32 * Steve Reinhardt
33 * Stephen Hines
34 * Timothy M. Jones
35 */
36
37#ifndef __ARCH_POWER_TLB_HH__
38#define __ARCH_POWER_TLB_HH__
39
40#include <map>
41
42#include "arch/generic/tlb.hh"
43#include "arch/power/isa_traits.hh"
44#include "arch/power/pagetable.hh"
45#include "arch/power/utility.hh"
46#include "arch/power/vtophys.hh"
47#include "base/statistics.hh"
48#include "mem/request.hh"
49#include "params/PowerTLB.hh"
50
51class ThreadContext;
52
53namespace PowerISA {
54
55// This is copied from the ARM ISA and has not been checked against the
56// Power at all.
57struct TlbEntry
58{
59 Addr _pageStart;
60
61 TlbEntry()
62 {
63 }
64
65 TlbEntry(Addr asn, Addr vaddr, Addr paddr,
66 bool uncacheable, bool read_only)
67 : _pageStart(paddr)
68 {
69 if (uncacheable || read_only)
70 warn("Power TlbEntry does not support uncacheable"
71 " or read-only mappings\n");
72 }
73
74 void
75 updateVaddr(Addr new_vaddr)
76 {
77 panic("unimplemented");
78 }
79
80 Addr
81 pageStart()
82 {
83 return _pageStart;
84 }
85
86 void
87 serialize(CheckpointOut &cp) const
88 {
89 SERIALIZE_SCALAR(_pageStart);
90 }
91
92 void
93 unserialize(CheckpointIn &cp)
94 {
95 UNSERIALIZE_SCALAR(_pageStart);
96 }
97};
98
99class TLB : public BaseTLB
100{
101 protected:
102 typedef std::multimap<Addr, int> PageTable;
103 PageTable lookupTable; // Quick lookup into page table
104
105 PowerISA::PTE *table; // the Page Table
106 int size; // TLB Size
107 int nlu; // not last used entry (for replacement)
108
109 void
110 nextnlu()
111 {
112 if (++nlu >= size) {
113 nlu = 0;
114 }
115 }
116
117 PowerISA::PTE *lookup(Addr vpn, uint8_t asn) const;
118
119 mutable Stats::Scalar read_hits;
120 mutable Stats::Scalar read_misses;
121 mutable Stats::Scalar read_acv;
122 mutable Stats::Scalar read_accesses;
123 mutable Stats::Scalar write_hits;
124 mutable Stats::Scalar write_misses;
125 mutable Stats::Scalar write_acv;
126 mutable Stats::Scalar write_accesses;
127 Stats::Formula hits;
128 Stats::Formula misses;
129 Stats::Formula accesses;
130
131 public:
132 typedef PowerTLBParams Params;
133 TLB(const Params *p);
134 virtual ~TLB();
135
136 void takeOverFrom(BaseTLB *otlb) override {}
137
138 int probeEntry(Addr vpn,uint8_t) const;
139 PowerISA::PTE *getEntry(unsigned) const;
140
141 int smallPages;
142
143 int
144 getsize() const
145 {
146 return size;
147 }
148
149 PowerISA::PTE &index(bool advance = true);
150 void insert(Addr vaddr, PowerISA::PTE &pte);
151 void insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages);
152 void flushAll() override;
153
154 void
155 demapPage(Addr vaddr, uint64_t asn) override
156 {
157 panic("demapPage unimplemented.\n");
158 }
159
160 // static helper functions... really
161 static bool validVirtualAddress(Addr vaddr);
162 static Fault checkCacheability(RequestPtr &req);
163 Fault translateInst(RequestPtr req, ThreadContext *tc);
164 Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
|
165 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
166 void translateTiming(RequestPtr req, ThreadContext *tc,
167 Translation *translation, Mode mode);
168 /** Stub function for CheckerCPU compilation support. Power ISA not
169 * supported by Checker at the moment
170 */
171 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
172 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
| 165 Fault translateAtomic(
166 RequestPtr req, ThreadContext *tc, Mode mode) override;
167 void translateTiming(
168 RequestPtr req, ThreadContext *tc,
169 Translation *translation, Mode mode) override;
170 Fault finalizePhysical(
171 RequestPtr req, ThreadContext *tc, Mode mode) const override;
|