registers.hh (9918:2c7219e2d999) registers.hh (9920:028e4da64b42)
1/*
2 * Copyright (c) 2009 The University of Edinburgh
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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47
48typedef uint64_t IntReg;
49
50// Floating point register file entry type
51typedef uint64_t FloatRegBits;
52typedef double FloatReg;
53typedef uint64_t MiscReg;
54
1/*
2 * Copyright (c) 2009 The University of Edinburgh
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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47
48typedef uint64_t IntReg;
49
50// Floating point register file entry type
51typedef uint64_t FloatRegBits;
52typedef double FloatReg;
53typedef uint64_t MiscReg;
54
55// dummy typedef since we don't have CC regs
56typedef uint8_t CCReg;
57
55// Constants Related to the number of registers
56const int NumIntArchRegs = 32;
57
58// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
59// and zero register, which doesn't actually exist but needs a number
60const int NumIntSpecialRegs = 9;
61const int NumFloatArchRegs = 32;
62const int NumFloatSpecialRegs = 0;
63const int NumInternalProcRegs = 0;
64
65const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
66const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
58// Constants Related to the number of registers
59const int NumIntArchRegs = 32;
60
61// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
62// and zero register, which doesn't actually exist but needs a number
63const int NumIntSpecialRegs = 9;
64const int NumFloatArchRegs = 32;
65const int NumFloatSpecialRegs = 0;
66const int NumInternalProcRegs = 0;
67
68const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
69const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
70const int NumCCRegs = 0;
67const int NumMiscRegs = NUM_MISCREGS;
68
69// Semantically meaningful register indices
70const int ReturnValueReg = 3;
71const int ArgumentReg0 = 3;
72const int ArgumentReg1 = 4;
73const int ArgumentReg2 = 5;
74const int ArgumentReg3 = 6;

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80const int ZeroReg = NumIntRegs - 1;
81
82const int SyscallNumReg = 0;
83const int SyscallPseudoReturnReg = 3;
84const int SyscallSuccessReg = 3;
85
86// These help enumerate all the registers for dependence tracking.
87const int FP_Reg_Base = NumIntRegs;
71const int NumMiscRegs = NUM_MISCREGS;
72
73// Semantically meaningful register indices
74const int ReturnValueReg = 3;
75const int ArgumentReg0 = 3;
76const int ArgumentReg1 = 4;
77const int ArgumentReg2 = 5;
78const int ArgumentReg3 = 6;

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84const int ZeroReg = NumIntRegs - 1;
85
86const int SyscallNumReg = 0;
87const int SyscallPseudoReturnReg = 3;
88const int SyscallSuccessReg = 3;
89
90// These help enumerate all the registers for dependence tracking.
91const int FP_Reg_Base = NumIntRegs;
88const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs;
92const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
93const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
89const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
90
91typedef union {
92 IntReg intreg;
93 FloatReg fpreg;
94 MiscReg ctrlreg;
95} AnyReg;
96

--- 14 unchanged lines hidden --- 		94const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
95
96typedef union {
97 IntReg intreg;
98 FloatReg fpreg;
99 MiscReg ctrlreg;
100} AnyReg;
101

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