registers.hh (13592:b8972ccebd63) registers.hh (13610:5d5404ac6288)
1/*
2 * Copyright (c) 2009 The University of Edinburgh
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Timothy M. Jones
29 */
30
31#ifndef __ARCH_POWER_REGISTERS_HH__
32#define __ARCH_POWER_REGISTERS_HH__
33
1/*
2 * Copyright (c) 2009 The University of Edinburgh
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Timothy M. Jones
29 */
30
31#ifndef __ARCH_POWER_REGISTERS_HH__
32#define __ARCH_POWER_REGISTERS_HH__
33
34#include "arch/generic/vec_pred_reg.hh"
34#include "arch/generic/vec_reg.hh"
35#include "arch/power/generated/max_inst_regs.hh"
36#include "arch/power/miscregs.hh"
37#include "base/types.hh"
38
39namespace PowerISA {
40
41using PowerISAInst::MaxInstSrcRegs;

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49
50// Floating point register file entry type
51typedef RegVal FloatRegBits;
52typedef RegVal MiscReg;
53
54// dummy typedef since we don't have CC regs
55typedef uint8_t CCReg;
56
35#include "arch/generic/vec_reg.hh"
36#include "arch/power/generated/max_inst_regs.hh"
37#include "arch/power/miscregs.hh"
38#include "base/types.hh"
39
40namespace PowerISA {
41
42using PowerISAInst::MaxInstSrcRegs;

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50
51// Floating point register file entry type
52typedef RegVal FloatRegBits;
53typedef RegVal MiscReg;
54
55// dummy typedef since we don't have CC regs
56typedef uint8_t CCReg;
57
57// dummy typedefs since we don't have vector regs
58constexpr unsigned NumVecElemPerVecReg = 2;
59using VecElem = uint32_t;
60using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
61using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
62using VecRegContainer = VecReg::Container;
63// This has to be one to prevent warnings that are treated as errors
64constexpr unsigned NumVecRegs = 1;
58// Not applicable to Power
59using VecElem = ::DummyVecElem;
60using VecReg = ::DummyVecReg;
61using ConstVecReg = ::DummyConstVecReg;
62using VecRegContainer = ::DummyVecRegContainer;
63constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
64constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
65
65
66// Not applicable to Power
67using VecPredReg = ::DummyVecPredReg;
68using ConstVecPredReg = ::DummyConstVecPredReg;
69using VecPredRegContainer = ::DummyVecPredRegContainer;
70constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
71constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
72
66// Constants Related to the number of registers
67const int NumIntArchRegs = 32;
68
69// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
70// and zero register, which doesn't actually exist but needs a number
71const int NumIntSpecialRegs = 9;
72const int NumFloatArchRegs = 32;
73const int NumFloatSpecialRegs = 0;
74const int NumInternalProcRegs = 0;
75
76const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
77const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
73// Constants Related to the number of registers
74const int NumIntArchRegs = 32;
75
76// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
77// and zero register, which doesn't actually exist but needs a number
78const int NumIntSpecialRegs = 9;
79const int NumFloatArchRegs = 32;
80const int NumFloatSpecialRegs = 0;
81const int NumInternalProcRegs = 0;
82
83const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
84const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
85const int NumVecRegs = 1; // Not applicable to Power
86 // (1 to prevent warnings)
87const int NumVecPredRegs = 1; // Not applicable to Power
88 // (1 to prevent warnings)
78const int NumCCRegs = 0;
79const int NumMiscRegs = NUM_MISCREGS;
80
81// Semantically meaningful register indices
82const int ReturnValueReg = 3;
83const int ArgumentReg0 = 3;
84const int ArgumentReg1 = 4;
85const int ArgumentReg2 = 5;

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90const int NumMiscRegs = NUM_MISCREGS;
91
92// Semantically meaningful register indices
93const int ReturnValueReg = 3;
94const int ArgumentReg0 = 3;
95const int ArgumentReg1 = 4;
96const int ArgumentReg2 = 5;

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