registers.hh (12109:f29e9c5418aa) | registers.hh (13338:c59f7e47e31d) |
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1/* 2 * Copyright (c) 2009 The University of Edinburgh 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 81 unchanged lines hidden (view full) --- 90 91// There isn't one in Power, but we need to define one somewhere 92const int ZeroReg = NumIntRegs - 1; 93 94const int SyscallNumReg = 0; 95const int SyscallPseudoReturnReg = 3; 96const int SyscallSuccessReg = 3; 97 | 1/* 2 * Copyright (c) 2009 The University of Edinburgh 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 81 unchanged lines hidden (view full) --- 90 91// There isn't one in Power, but we need to define one somewhere 92const int ZeroReg = NumIntRegs - 1; 93 94const int SyscallNumReg = 0; 95const int SyscallPseudoReturnReg = 3; 96const int SyscallSuccessReg = 3; 97 |
98typedef union { 99 IntReg intreg; 100 FloatReg fpreg; 101 MiscReg ctrlreg; 102} AnyReg; 103 | |
104enum MiscIntRegNums { 105 INTREG_CR = NumIntArchRegs, 106 INTREG_XER, 107 INTREG_LR, 108 INTREG_CTR, 109 INTREG_FPSCR, 110 INTREG_RSV, 111 INTREG_RSV_LEN, 112 INTREG_RSV_ADDR 113}; 114 115} // namespace PowerISA 116 117#endif // __ARCH_POWER_REGISTERS_HH__ | 98enum MiscIntRegNums { 99 INTREG_CR = NumIntArchRegs, 100 INTREG_XER, 101 INTREG_LR, 102 INTREG_CTR, 103 INTREG_FPSCR, 104 INTREG_RSV, 105 INTREG_RSV_LEN, 106 INTREG_RSV_ADDR 107}; 108 109} // namespace PowerISA 110 111#endif // __ARCH_POWER_REGISTERS_HH__ |