registers.hh (10934:5af8f40d8f2c) registers.hh (10935:acd48ddd725f)
1/*
2 * Copyright (c) 2009 The University of Edinburgh
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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50// Floating point register file entry type
51typedef uint64_t FloatRegBits;
52typedef double FloatReg;
53typedef uint64_t MiscReg;
54
55// dummy typedef since we don't have CC regs
56typedef uint8_t CCReg;
57
1/*
2 * Copyright (c) 2009 The University of Edinburgh
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 41 unchanged lines hidden (view full) ---

50// Floating point register file entry type
51typedef uint64_t FloatRegBits;
52typedef double FloatReg;
53typedef uint64_t MiscReg;
54
55// dummy typedef since we don't have CC regs
56typedef uint8_t CCReg;
57
58// typedefs for Vector registers
59const int NumVectorRegElements = 0;
60typedef uint64_t VectorRegElement;
61const int VectorRegBytes = NumVectorRegElements * sizeof(VectorRegElement);
62typedef std::array<VectorRegElement, NumVectorRegElements> VectorReg;
63
64// Constants Related to the number of registers
65const int NumIntArchRegs = 32;
66
67// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
68// and zero register, which doesn't actually exist but needs a number
69const int NumIntSpecialRegs = 9;
70const int NumFloatArchRegs = 32;
71const int NumFloatSpecialRegs = 0;
72const int NumInternalProcRegs = 0;
73
74const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
75const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
76const int NumCCRegs = 0;
58// Constants Related to the number of registers
59const int NumIntArchRegs = 32;
60
61// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
62// and zero register, which doesn't actually exist but needs a number
63const int NumIntSpecialRegs = 9;
64const int NumFloatArchRegs = 32;
65const int NumFloatSpecialRegs = 0;
66const int NumInternalProcRegs = 0;
67
68const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
69const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
70const int NumCCRegs = 0;
77const int NumVectorRegs = 0;
78const int NumMiscRegs = NUM_MISCREGS;
79
80// Semantically meaningful register indices
81const int ReturnValueReg = 3;
82const int ArgumentReg0 = 3;
83const int ArgumentReg1 = 4;
84const int ArgumentReg2 = 5;
85const int ArgumentReg3 = 6;

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92
93const int SyscallNumReg = 0;
94const int SyscallPseudoReturnReg = 3;
95const int SyscallSuccessReg = 3;
96
97// These help enumerate all the registers for dependence tracking.
98const int FP_Reg_Base = NumIntRegs;
99const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
71const int NumMiscRegs = NUM_MISCREGS;
72
73// Semantically meaningful register indices
74const int ReturnValueReg = 3;
75const int ArgumentReg0 = 3;
76const int ArgumentReg1 = 4;
77const int ArgumentReg2 = 5;
78const int ArgumentReg3 = 6;

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85
86const int SyscallNumReg = 0;
87const int SyscallPseudoReturnReg = 3;
88const int SyscallSuccessReg = 3;
89
90// These help enumerate all the registers for dependence tracking.
91const int FP_Reg_Base = NumIntRegs;
92const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs;
100const int Vector_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
101const int Misc_Reg_Base = Vector_Reg_Base + NumVectorRegs; // NumVectorRegs == 0
93const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0
102const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
103
104typedef union {
105 IntReg intreg;
106 FloatReg fpreg;
107 MiscReg ctrlreg;
108} AnyReg;
109

--- 14 unchanged lines hidden --- 		94const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs;
95
96typedef union {
97 IntReg intreg;
98 FloatReg fpreg;
99 MiscReg ctrlreg;
100} AnyReg;
101

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