1/* 2 * Copyright (c) 2009 The University of Edinburgh 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Timothy M. Jones 29 */ 30 31#ifndef __ARCH_POWER_REGISTERS_HH__ 32#define __ARCH_POWER_REGISTERS_HH__ 33 34#include "arch/generic/vec_pred_reg.hh" 35#include "arch/generic/vec_reg.hh" 36#include "arch/power/generated/max_inst_regs.hh" 37#include "arch/power/miscregs.hh" 38#include "base/types.hh" 39 40namespace PowerISA { 41 42using PowerISAInst::MaxInstSrcRegs; 43using PowerISAInst::MaxInstDestRegs; 44 45// Power writes a misc register outside of the isa parser, so it can't 46// be detected by it. Manually add it here. 47const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1; 48 |
49// dummy typedef since we don't have CC regs 50typedef uint8_t CCReg; 51 52// Not applicable to Power 53using VecElem = ::DummyVecElem; 54using VecReg = ::DummyVecReg; 55using ConstVecReg = ::DummyConstVecReg; 56using VecRegContainer = ::DummyVecRegContainer; 57constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg; 58constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes; 59 60// Not applicable to Power 61using VecPredReg = ::DummyVecPredReg; 62using ConstVecPredReg = ::DummyConstVecPredReg; 63using VecPredRegContainer = ::DummyVecPredRegContainer; 64constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits; 65constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr; 66 67// Constants Related to the number of registers 68const int NumIntArchRegs = 32; 69 70// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR 71// and zero register, which doesn't actually exist but needs a number 72const int NumIntSpecialRegs = 9; 73const int NumFloatArchRegs = 32; 74const int NumFloatSpecialRegs = 0; 75const int NumInternalProcRegs = 0; 76 77const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; 78const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; 79const int NumVecRegs = 1; // Not applicable to Power 80 // (1 to prevent warnings) 81const int NumVecPredRegs = 1; // Not applicable to Power 82 // (1 to prevent warnings) 83const int NumCCRegs = 0; 84const int NumMiscRegs = NUM_MISCREGS; 85 86// Semantically meaningful register indices 87const int ReturnValueReg = 3; 88const int ArgumentReg0 = 3; 89const int ArgumentReg1 = 4; 90const int ArgumentReg2 = 5; 91const int ArgumentReg3 = 6; 92const int ArgumentReg4 = 7; 93const int FramePointerReg = 31; 94const int StackPointerReg = 1; 95 96// There isn't one in Power, but we need to define one somewhere 97const int ZeroReg = NumIntRegs - 1; 98 99const int SyscallNumReg = 0; 100const int SyscallPseudoReturnReg = 3; 101const int SyscallSuccessReg = 3; 102 103enum MiscIntRegNums { 104 INTREG_CR = NumIntArchRegs, 105 INTREG_XER, 106 INTREG_LR, 107 INTREG_CTR, 108 INTREG_FPSCR, 109 INTREG_RSV, 110 INTREG_RSV_LEN, 111 INTREG_RSV_ADDR 112}; 113 114} // namespace PowerISA 115 116#endif // __ARCH_POWER_REGISTERS_HH__ |