1/* 2 * Copyright (c) 2009 The University of Edinburgh 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Timothy M. Jones 29 */ 30 31#ifndef __ARCH_POWER_REGISTERS_HH__ 32#define __ARCH_POWER_REGISTERS_HH__ 33 |
34#include "arch/generic/vec_pred_reg.hh" |
35#include "arch/generic/vec_reg.hh" 36#include "arch/power/generated/max_inst_regs.hh" 37#include "arch/power/miscregs.hh" 38#include "base/types.hh" 39 40namespace PowerISA { 41 42using PowerISAInst::MaxInstSrcRegs; --- 7 unchanged lines hidden (view full) --- 50 51// Floating point register file entry type 52typedef RegVal FloatRegBits; 53typedef RegVal MiscReg; 54 55// dummy typedef since we don't have CC regs 56typedef uint8_t CCReg; 57 |
58// Not applicable to Power 59using VecElem = ::DummyVecElem; 60using VecReg = ::DummyVecReg; 61using ConstVecReg = ::DummyConstVecReg; 62using VecRegContainer = ::DummyVecRegContainer; 63constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg; 64constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes; |
65 |
66// Not applicable to Power 67using VecPredReg = ::DummyVecPredReg; 68using ConstVecPredReg = ::DummyConstVecPredReg; 69using VecPredRegContainer = ::DummyVecPredRegContainer; 70constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits; 71constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr; 72 |
73// Constants Related to the number of registers 74const int NumIntArchRegs = 32; 75 76// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR 77// and zero register, which doesn't actually exist but needs a number 78const int NumIntSpecialRegs = 9; 79const int NumFloatArchRegs = 32; 80const int NumFloatSpecialRegs = 0; 81const int NumInternalProcRegs = 0; 82 83const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; 84const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; |
85const int NumVecRegs = 1; // Not applicable to Power 86 // (1 to prevent warnings) 87const int NumVecPredRegs = 1; // Not applicable to Power 88 // (1 to prevent warnings) |
89const int NumCCRegs = 0; 90const int NumMiscRegs = NUM_MISCREGS; 91 92// Semantically meaningful register indices 93const int ReturnValueReg = 3; 94const int ArgumentReg0 = 3; 95const int ArgumentReg1 = 4; 96const int ArgumentReg2 = 5; --- 26 unchanged lines hidden --- |