1/* 2 * Copyright (c) 2009 The University of Edinburgh 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 20 unchanged lines hidden (view full) --- 29 */ 30 31#ifndef __ARCH_POWER_REGISTERS_HH__ 32#define __ARCH_POWER_REGISTERS_HH__ 33 34#include "arch/generic/vec_reg.hh" 35#include "arch/power/generated/max_inst_regs.hh" 36#include "arch/power/miscregs.hh" |
37#include "base/types.hh" |
38 39namespace PowerISA { 40 41using PowerISAInst::MaxInstSrcRegs; 42using PowerISAInst::MaxInstDestRegs; 43 44// Power writes a misc register outside of the isa parser, so it can't 45// be detected by it. Manually add it here. 46const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1; 47 |
48typedef RegVal IntReg; |
49 50// Floating point register file entry type |
51typedef RegVal FloatRegBits; 52typedef FloatRegVal FloatReg; 53typedef RegVal MiscReg; |
54 55// dummy typedef since we don't have CC regs 56typedef uint8_t CCReg; 57 58// dummy typedefs since we don't have vector regs 59constexpr unsigned NumVecElemPerVecReg = 2; 60using VecElem = uint32_t; 61using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; --- 51 unchanged lines hidden --- |