1/* 2 * Copyright (c) 2009 The University of Edinburgh 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Timothy M. Jones 29 */ 30 31#ifndef __ARCH_POWER_REGISTERS_HH__ 32#define __ARCH_POWER_REGISTERS_HH__ 33 34#include "arch/power/generated/max_inst_regs.hh" 35#include "arch/power/miscregs.hh" 36 37namespace PowerISA { 38 39using PowerISAInst::MaxInstSrcRegs; 40using PowerISAInst::MaxInstDestRegs;
| 1/* 2 * Copyright (c) 2009 The University of Edinburgh 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Timothy M. Jones 29 */ 30 31#ifndef __ARCH_POWER_REGISTERS_HH__ 32#define __ARCH_POWER_REGISTERS_HH__ 33 34#include "arch/power/generated/max_inst_regs.hh" 35#include "arch/power/miscregs.hh" 36 37namespace PowerISA { 38 39using PowerISAInst::MaxInstSrcRegs; 40using PowerISAInst::MaxInstDestRegs;
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43typedef uint8_t RegIndex; 44 45typedef uint64_t IntReg; 46 47// Floating point register file entry type 48typedef uint64_t FloatRegBits; 49typedef double FloatReg; 50typedef uint64_t MiscReg; 51 52// Constants Related to the number of registers 53const int NumIntArchRegs = 32; 54 55// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR 56// and zero register, which doesn't actually exist but needs a number 57const int NumIntSpecialRegs = 9; 58const int NumFloatArchRegs = 32; 59const int NumFloatSpecialRegs = 0; 60const int NumInternalProcRegs = 0; 61 62const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; 63const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; 64const int NumMiscRegs = NUM_MISCREGS; 65 66// Semantically meaningful register indices 67const int ReturnValueReg = 3; 68const int ArgumentReg0 = 3; 69const int ArgumentReg1 = 4; 70const int ArgumentReg2 = 5; 71const int ArgumentReg3 = 6; 72const int ArgumentReg4 = 7; 73const int FramePointerReg = 31; 74const int StackPointerReg = 1; 75 76// There isn't one in Power, but we need to define one somewhere 77const int ZeroReg = NumIntRegs - 1; 78 79const int SyscallNumReg = 0; 80const int SyscallPseudoReturnReg = 3; 81const int SyscallSuccessReg = 3; 82 83// These help enumerate all the registers for dependence tracking. 84const int FP_Base_DepTag = NumIntRegs; 85const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; 86const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs; 87 88typedef union { 89 IntReg intreg; 90 FloatReg fpreg; 91 MiscReg ctrlreg; 92} AnyReg; 93 94enum MiscIntRegNums { 95 INTREG_CR = NumIntArchRegs, 96 INTREG_XER, 97 INTREG_LR, 98 INTREG_CTR, 99 INTREG_FPSCR, 100 INTREG_RSV, 101 INTREG_RSV_LEN, 102 INTREG_RSV_ADDR 103}; 104 105} // namespace PowerISA 106 107#endif // __ARCH_POWER_REGISTERS_HH__
| 46typedef uint8_t RegIndex; 47 48typedef uint64_t IntReg; 49 50// Floating point register file entry type 51typedef uint64_t FloatRegBits; 52typedef double FloatReg; 53typedef uint64_t MiscReg; 54 55// Constants Related to the number of registers 56const int NumIntArchRegs = 32; 57 58// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR 59// and zero register, which doesn't actually exist but needs a number 60const int NumIntSpecialRegs = 9; 61const int NumFloatArchRegs = 32; 62const int NumFloatSpecialRegs = 0; 63const int NumInternalProcRegs = 0; 64 65const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; 66const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; 67const int NumMiscRegs = NUM_MISCREGS; 68 69// Semantically meaningful register indices 70const int ReturnValueReg = 3; 71const int ArgumentReg0 = 3; 72const int ArgumentReg1 = 4; 73const int ArgumentReg2 = 5; 74const int ArgumentReg3 = 6; 75const int ArgumentReg4 = 7; 76const int FramePointerReg = 31; 77const int StackPointerReg = 1; 78 79// There isn't one in Power, but we need to define one somewhere 80const int ZeroReg = NumIntRegs - 1; 81 82const int SyscallNumReg = 0; 83const int SyscallPseudoReturnReg = 3; 84const int SyscallSuccessReg = 3; 85 86// These help enumerate all the registers for dependence tracking. 87const int FP_Base_DepTag = NumIntRegs; 88const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs; 89const int Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs; 90 91typedef union { 92 IntReg intreg; 93 FloatReg fpreg; 94 MiscReg ctrlreg; 95} AnyReg; 96 97enum MiscIntRegNums { 98 INTREG_CR = NumIntArchRegs, 99 INTREG_XER, 100 INTREG_LR, 101 INTREG_CTR, 102 INTREG_FPSCR, 103 INTREG_RSV, 104 INTREG_RSV_LEN, 105 INTREG_RSV_ADDR 106}; 107 108} // namespace PowerISA 109 110#endif // __ARCH_POWER_REGISTERS_HH__
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