1/* 2 * Copyright (c) 2009 The University of Edinburgh 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Timothy M. Jones 29 */ 30 31#ifndef __ARCH_POWER_REGISTERS_HH__ 32#define __ARCH_POWER_REGISTERS_HH__ 33 34#include "arch/generic/vec_reg.hh" 35#include "arch/power/generated/max_inst_regs.hh" 36#include "arch/power/miscregs.hh"
| 1/* 2 * Copyright (c) 2009 The University of Edinburgh 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Timothy M. Jones 29 */ 30 31#ifndef __ARCH_POWER_REGISTERS_HH__ 32#define __ARCH_POWER_REGISTERS_HH__ 33 34#include "arch/generic/vec_reg.hh" 35#include "arch/power/generated/max_inst_regs.hh" 36#include "arch/power/miscregs.hh"
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| 37#include "base/types.hh"
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37 38namespace PowerISA { 39 40using PowerISAInst::MaxInstSrcRegs; 41using PowerISAInst::MaxInstDestRegs; 42 43// Power writes a misc register outside of the isa parser, so it can't 44// be detected by it. Manually add it here. 45const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1; 46
| 38 39namespace PowerISA { 40 41using PowerISAInst::MaxInstSrcRegs; 42using PowerISAInst::MaxInstDestRegs; 43 44// Power writes a misc register outside of the isa parser, so it can't 45// be detected by it. Manually add it here. 46const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1; 47
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47typedef uint64_t IntReg;
| 48typedef RegVal IntReg;
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48 49// Floating point register file entry type
| 49 50// Floating point register file entry type
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50typedef uint64_t FloatRegBits; 51typedef double FloatReg; 52typedef uint64_t MiscReg;
| 51typedef RegVal FloatRegBits; 52typedef FloatRegVal FloatReg; 53typedef RegVal MiscReg;
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53 54// dummy typedef since we don't have CC regs 55typedef uint8_t CCReg; 56 57// dummy typedefs since we don't have vector regs 58constexpr unsigned NumVecElemPerVecReg = 2; 59using VecElem = uint32_t; 60using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 61using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 62using VecRegContainer = VecReg::Container; 63// This has to be one to prevent warnings that are treated as errors 64constexpr unsigned NumVecRegs = 1; 65 66// Constants Related to the number of registers 67const int NumIntArchRegs = 32; 68 69// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR 70// and zero register, which doesn't actually exist but needs a number 71const int NumIntSpecialRegs = 9; 72const int NumFloatArchRegs = 32; 73const int NumFloatSpecialRegs = 0; 74const int NumInternalProcRegs = 0; 75 76const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; 77const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; 78const int NumCCRegs = 0; 79const int NumMiscRegs = NUM_MISCREGS; 80 81// Semantically meaningful register indices 82const int ReturnValueReg = 3; 83const int ArgumentReg0 = 3; 84const int ArgumentReg1 = 4; 85const int ArgumentReg2 = 5; 86const int ArgumentReg3 = 6; 87const int ArgumentReg4 = 7; 88const int FramePointerReg = 31; 89const int StackPointerReg = 1; 90 91// There isn't one in Power, but we need to define one somewhere 92const int ZeroReg = NumIntRegs - 1; 93 94const int SyscallNumReg = 0; 95const int SyscallPseudoReturnReg = 3; 96const int SyscallSuccessReg = 3; 97 98enum MiscIntRegNums { 99 INTREG_CR = NumIntArchRegs, 100 INTREG_XER, 101 INTREG_LR, 102 INTREG_CTR, 103 INTREG_FPSCR, 104 INTREG_RSV, 105 INTREG_RSV_LEN, 106 INTREG_RSV_ADDR 107}; 108 109} // namespace PowerISA 110 111#endif // __ARCH_POWER_REGISTERS_HH__
| 54 55// dummy typedef since we don't have CC regs 56typedef uint8_t CCReg; 57 58// dummy typedefs since we don't have vector regs 59constexpr unsigned NumVecElemPerVecReg = 2; 60using VecElem = uint32_t; 61using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 62using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 63using VecRegContainer = VecReg::Container; 64// This has to be one to prevent warnings that are treated as errors 65constexpr unsigned NumVecRegs = 1; 66 67// Constants Related to the number of registers 68const int NumIntArchRegs = 32; 69 70// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR 71// and zero register, which doesn't actually exist but needs a number 72const int NumIntSpecialRegs = 9; 73const int NumFloatArchRegs = 32; 74const int NumFloatSpecialRegs = 0; 75const int NumInternalProcRegs = 0; 76 77const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; 78const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; 79const int NumCCRegs = 0; 80const int NumMiscRegs = NUM_MISCREGS; 81 82// Semantically meaningful register indices 83const int ReturnValueReg = 3; 84const int ArgumentReg0 = 3; 85const int ArgumentReg1 = 4; 86const int ArgumentReg2 = 5; 87const int ArgumentReg3 = 6; 88const int ArgumentReg4 = 7; 89const int FramePointerReg = 31; 90const int StackPointerReg = 1; 91 92// There isn't one in Power, but we need to define one somewhere 93const int ZeroReg = NumIntRegs - 1; 94 95const int SyscallNumReg = 0; 96const int SyscallPseudoReturnReg = 3; 97const int SyscallSuccessReg = 3; 98 99enum MiscIntRegNums { 100 INTREG_CR = NumIntArchRegs, 101 INTREG_XER, 102 INTREG_LR, 103 INTREG_CTR, 104 INTREG_FPSCR, 105 INTREG_RSV, 106 INTREG_RSV_LEN, 107 INTREG_RSV_ADDR 108}; 109 110} // namespace PowerISA 111 112#endif // __ARCH_POWER_REGISTERS_HH__
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