1/* 2 * Copyright (c) 2007-2008 The Florida State University 3 * Copyright (c) 2009 The University of Edinburgh 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 33 unchanged lines hidden (view full) --- 42#include "mem/page_table.hh" 43#include "sim/process_impl.hh" 44#include "sim/syscall_return.hh" 45#include "sim/system.hh" 46 47using namespace std; 48using namespace PowerISA; 49 |
50PowerProcess::PowerProcess(ProcessParams *params, ObjectFile *objFile) 51 : Process(params, objFile) |
52{ 53 stack_base = 0xbf000000L; 54 55 // Set pointer for next thread stack. Reserve 8M for main stack. 56 next_thread_stack_base = stack_base - (8 * 1024 * 1024); 57 58 // Set up break point (Top of Heap) 59 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 60 brk_point = roundUp(brk_point, PageBytes); 61 62 // Set up region for mmaps. For now, start at bottom of kuseg space. 63 mmap_end = 0x70000000L; 64} 65 66void |
67PowerProcess::initState() |
68{ 69 Process::initState(); 70 71 argsInit(MachineBytes, PageBytes); 72} 73 74void |
75PowerProcess::argsInit(int intSize, int pageSize) |
76{ 77 typedef AuxVector<uint32_t> auxv_t; 78 std::vector<auxv_t> auxv; 79 80 string filename; 81 if (argv.size() < 1) 82 filename = ""; 83 else --- 176 unchanged lines hidden (view full) --- 260 261 tc->pcState(getStartPC()); 262 263 //Align the "stack_min" to a page boundary. 264 stack_min = roundDown(stack_min, pageSize); 265} 266 267PowerISA::IntReg |
268PowerProcess::getSyscallArg(ThreadContext *tc, int &i) |
269{ 270 assert(i < 5); 271 return tc->readIntReg(ArgumentReg0 + i++); 272} 273 274void |
275PowerProcess::setSyscallArg(ThreadContext *tc, int i, PowerISA::IntReg val) |
276{ 277 assert(i < 5); 278 tc->setIntReg(ArgumentReg0 + i, val); 279} 280 281void |
282PowerProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) |
283{ 284 Cr cr = tc->readIntReg(INTREG_CR); 285 if (sysret.successful()) { 286 cr.cr0.so = 0; 287 } else { 288 cr.cr0.so = 1; 289 } 290 tc->setIntReg(INTREG_CR, cr); 291 tc->setIntReg(ReturnValueReg, sysret.encodedValue()); 292} |