1/*
2 * Copyright (c) 2007-2008 The Florida State University
3 * Copyright (c) 2009 The University of Edinburgh
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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42#include "mem/page_table.hh"
43#include "sim/process_impl.hh"
44#include "sim/syscall_return.hh"
45#include "sim/system.hh"
46
47using namespace std;
48using namespace PowerISA;
49
50PowerLiveProcess::PowerLiveProcess(LiveProcessParams *params,
51 ObjectFile *objFile)
52 : LiveProcess(params, objFile)
53{
54 stack_base = 0xbf000000L;
55
56 // Set pointer for next thread stack. Reserve 8M for main stack.
57 next_thread_stack_base = stack_base - (8 * 1024 * 1024);
58
59 // Set up break point (Top of Heap)
60 brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
61 brk_point = roundUp(brk_point, PageBytes);
62
63 // Set up region for mmaps. For now, start at bottom of kuseg space.
64 mmap_end = 0x70000000L;
65}
66
67void
68PowerLiveProcess::initState()
69{
70 Process::initState();
71
72 argsInit(MachineBytes, PageBytes);
73}
74
75void
76PowerLiveProcess::argsInit(int intSize, int pageSize)
77{
78 typedef AuxVector<uint32_t> auxv_t;
79 std::vector<auxv_t> auxv;
80
81 string filename;
82 if (argv.size() < 1)
83 filename = "";
84 else

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261
262 tc->pcState(getStartPC());
263
264 //Align the "stack_min" to a page boundary.
265 stack_min = roundDown(stack_min, pageSize);
266}
267
268PowerISA::IntReg
269PowerLiveProcess::getSyscallArg(ThreadContext *tc, int &i)
270{
271 assert(i < 5);
272 return tc->readIntReg(ArgumentReg0 + i++);
273}
274
275void
276PowerLiveProcess::setSyscallArg(ThreadContext *tc,
277 int i, PowerISA::IntReg val)
278{
279 assert(i < 5);
280 tc->setIntReg(ArgumentReg0 + i, val);
281}
282
283void
284PowerLiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
285{
286 Cr cr = tc->readIntReg(INTREG_CR);
287 if (sysret.successful()) {
288 cr.cr0.so = 0;
289 } else {
290 cr.cr0.so = 1;
291 }
292 tc->setIntReg(INTREG_CR, cr);
293 tc->setIntReg(ReturnValueReg, sysret.encodedValue());
294}