mmapped_ipr.hh (9180:ee8d7a51651d) mmapped_ipr.hh (9897:e105fbf799e7)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * Copyright (c) 2009 The University of Edinburgh
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

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36#define __ARCH_POWER_MMAPPED_IPR_HH__
37
38/**
39 * @file
40 *
41 * ISA-specific helper functions for memory mapped IPR accesses.
42 */
43
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * Copyright (c) 2009 The University of Edinburgh
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

--- 27 unchanged lines hidden (view full) ---

36#define __ARCH_POWER_MMAPPED_IPR_HH__
37
38/**
39 * @file
40 *
41 * ISA-specific helper functions for memory mapped IPR accesses.
42 */
43
44#include "base/misc.hh"
45#include "mem/packet.hh"
44#include "arch/generic/mmapped_ipr.hh"
46
47class ThreadContext;
48
49namespace PowerISA
50{
45
46class ThreadContext;
47
48namespace PowerISA
49{
51
52inline Cycles
53handleIprRead(ThreadContext *xc, Packet *pkt)
54{
55 panic("No implementation for handleIprRead in POWER\n");
56}
57
58inline Cycles
59handleIprWrite(ThreadContext *xc, Packet *pkt)
60{
61 panic("No implementation for handleIprWrite in POWER\n");
62}
63
50 using GenericISA::handleIprRead;
51 using GenericISA::handleIprWrite;
64} // namespace PowerISA
65
66#endif // __ARCH_POWER_MMAPPED_IPR_HH__
52} // namespace PowerISA
53
54#endif // __ARCH_POWER_MMAPPED_IPR_HH__