isa_traits.hh (6974:4d4903a3e7c5) isa_traits.hh (7811:a8fc35183c10)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * Copyright (c) 2009 The University of Edinburgh
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

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33 */
34
35#ifndef __ARCH_POWER_ISA_TRAITS_HH__
36#define __ARCH_POWER_ISA_TRAITS_HH__
37
38#include "arch/power/types.hh"
39#include "base/types.hh"
40
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007-2008 The Florida State University
4 * Copyright (c) 2009 The University of Edinburgh
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

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33 */
34
35#ifndef __ARCH_POWER_ISA_TRAITS_HH__
36#define __ARCH_POWER_ISA_TRAITS_HH__
37
38#include "arch/power/types.hh"
39#include "base/types.hh"
40
41namespace BigEndianGuest {};
41namespace BigEndianGuest {}
42
43class StaticInstPtr;
44
45namespace PowerISA
46{
47
48using namespace BigEndianGuest;
49

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68const int MachineBytes = 4;
69
70// This is ori 0, 0, 0
71const ExtMachInst NoopMachInst = 0x60000000;
72
73// Memory accesses can be unaligned
74const bool HasUnalignedMemAcc = true;
75
42
43class StaticInstPtr;
44
45namespace PowerISA
46{
47
48using namespace BigEndianGuest;
49

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68const int MachineBytes = 4;
69
70// This is ori 0, 0, 0
71const ExtMachInst NoopMachInst = 0x60000000;
72
73// Memory accesses can be unaligned
74const bool HasUnalignedMemAcc = true;
75
76} // PowerISA namespace
76} // namespace PowerISA
77
78#endif // __ARCH_POWER_ISA_TRAITS_HH__
77
78#endif // __ARCH_POWER_ISA_TRAITS_HH__