operands.isa (6691:cd68b6ecd68d) operands.isa (7720:65d338a8dba4)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2009 The University of Edinburgh
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 45 unchanged lines hidden (view full) ---

54 'Fc': ('FloatReg', 'df', 'FRC', 'IsFloating', 3),
55 'Fs': ('FloatReg', 'df', 'FRS', 'IsFloating', 4),
56 'Ft': ('FloatReg', 'df', 'FRT', 'IsFloating', 5),
57
58 # Memory Operand
59 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
60
61 # Program counter and next
1// -*- mode:c++ -*-
2
3// Copyright (c) 2009 The University of Edinburgh
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 45 unchanged lines hidden (view full) ---

54 'Fc': ('FloatReg', 'df', 'FRC', 'IsFloating', 3),
55 'Fs': ('FloatReg', 'df', 'FRS', 'IsFloating', 4),
56 'Ft': ('FloatReg', 'df', 'FRT', 'IsFloating', 5),
57
58 # Memory Operand
59 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
60
61 # Program counter and next
62 'PC': ('PC', 'uw', None, (None, None, 'IsControl'), 9),
63 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 9),
62 'PCS': ('PCState', 'uq', None, (None, None, 'IsControl'), 9),
64
65 # Control registers
66 'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),
67 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
68 'CTR': ('IntReg', 'uw', 'INTREG_CTR', 'IsInteger', 9),
69 'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),
70
71 # Setting as IntReg so things are stored as an integer, not double
72 'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9),
73
74 # Registers for linked loads and stores
75 'Rsv': ('IntReg', 'uw', 'INTREG_RSV', 'IsInteger', 9),
76 'RsvLen': ('IntReg', 'uw', 'INTREG_RSV_LEN', 'IsInteger', 9),
77 'RsvAddr': ('IntReg', 'uw', 'INTREG_RSV_ADDR', 'IsInteger', 9),
78
79 # Hack for non-full-system syscall emulation
80 'R0': ('IntReg', 'uw', '0', None, 1),
81}};
63
64 # Control registers
65 'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),
66 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
67 'CTR': ('IntReg', 'uw', 'INTREG_CTR', 'IsInteger', 9),
68 'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),
69
70 # Setting as IntReg so things are stored as an integer, not double
71 'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9),
72
73 # Registers for linked loads and stores
74 'Rsv': ('IntReg', 'uw', 'INTREG_RSV', 'IsInteger', 9),
75 'RsvLen': ('IntReg', 'uw', 'INTREG_RSV_LEN', 'IsInteger', 9),
76 'RsvAddr': ('IntReg', 'uw', 'INTREG_RSV_ADDR', 'IsInteger', 9),
77
78 # Hack for non-full-system syscall emulation
79 'R0': ('IntReg', 'uw', '0', None, 1),
80}};