Cross Reference: /gem5/src/arch/power/isa/operands.isa

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operands.isa (13800:cffc4c0fc94e)	operands.isa (13801:e18de9c80ce3)
1// -- mode:c++ -- 2 3// Copyright (c) 2009 The University of Edinburgh 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 45 unchanged lines hidden (view full) --- 54 'Fc': ('FloatReg', 'df', 'FRC', 'IsFloating', 3), 55 'Fs': ('FloatReg', 'df', 'FRS', 'IsFloating', 4), 56 'Ft': ('FloatReg', 'df', 'FRT', 'IsFloating', 5), 57 58 # Memory Operand 59 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8), 60 61 # Program counter and next	1// -- mode:c++ -- 2 3// Copyright (c) 2009 The University of Edinburgh 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 45 unchanged lines hidden (view full) --- 54 'Fc': ('FloatReg', 'df', 'FRC', 'IsFloating', 3), 55 'Fs': ('FloatReg', 'df', 'FRS', 'IsFloating', 4), 56 'Ft': ('FloatReg', 'df', 'FRT', 'IsFloating', 5), 57 58 # Memory Operand 59 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8), 60 61 # Program counter and next
62 'PC': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 9), 63 'NPC': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 9),	62 'CIA': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 9), 63 'NIA': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 9),
64 65 # Control registers 66 'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9), 67 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), 68 'CTR': ('IntReg', 'uw', 'INTREG_CTR', 'IsInteger', 9), 69 'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9), 70 71 # Setting as IntReg so things are stored as an integer, not double 72 'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9), 73 74 # Registers for linked loads and stores 75 'Rsv': ('IntReg', 'uw', 'INTREG_RSV', 'IsInteger', 9), 76 'RsvLen': ('IntReg', 'uw', 'INTREG_RSV_LEN', 'IsInteger', 9), 77 'RsvAddr': ('IntReg', 'uw', 'INTREG_RSV_ADDR', 'IsInteger', 9), 78 79 # Hack for non-full-system syscall emulation 80 'R0': ('IntReg', 'uw', '0', None, 1), 81}};	64 65 # Control registers 66 'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9), 67 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), 68 'CTR': ('IntReg', 'uw', 'INTREG_CTR', 'IsInteger', 9), 69 'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9), 70 71 # Setting as IntReg so things are stored as an integer, not double 72 'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9), 73 74 # Registers for linked loads and stores 75 'Rsv': ('IntReg', 'uw', 'INTREG_RSV', 'IsInteger', 9), 76 'RsvLen': ('IntReg', 'uw', 'INTREG_RSV_LEN', 'IsInteger', 9), 77 'RsvAddr': ('IntReg', 'uw', 'INTREG_RSV_ADDR', 'IsInteger', 9), 78 79 # Hack for non-full-system syscall emulation 80 'R0': ('IntReg', 'uw', '0', None, 1), 81}};