1// -*- mode:c++ -*-
2
3// Copyright (c) 2009 The University of Edinburgh
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Timothy M. Jones
30
31def operand_types {{
32 'sb' : ('signed int', 8),
33 'ub' : ('unsigned int', 8),
34 'sh' : ('signed int', 16),
35 'uh' : ('unsigned int', 16),
36 'sw' : ('signed int', 32),
37 'uw' : ('unsigned int', 32),
38 'sq' : ('signed int', 64),
39 'uq' : ('unsigned int', 64),
40 'sf' : ('float', 32),
41 'df' : ('float', 64)
42}};
43
44def operands {{
45 # General Purpose Integer Reg Operands
46 'Ra': ('IntReg', 'uw', 'RA', 'IsInteger', 1),
47 'Rb': ('IntReg', 'uw', 'RB', 'IsInteger', 2),
48 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
49 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 4),
50
51 # General Purpose Floating Point Reg Operands
52 'Fa': ('FloatReg', 'df', 'FRA', 'IsFloating', 1),
53 'Fb': ('FloatReg', 'df', 'FRB', 'IsFloating', 2),
54 'Fc': ('FloatReg', 'df', 'FRC', 'IsFloating', 3),
55 'Fs': ('FloatReg', 'df', 'FRS', 'IsFloating', 4),
56 'Ft': ('FloatReg', 'df', 'FRT', 'IsFloating', 5),
57
58 # Memory Operand
59 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
60
61 # Program counter and next
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2009 The University of Edinburgh
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Timothy M. Jones
30
31def operand_types {{
32 'sb' : ('signed int', 8),
33 'ub' : ('unsigned int', 8),
34 'sh' : ('signed int', 16),
35 'uh' : ('unsigned int', 16),
36 'sw' : ('signed int', 32),
37 'uw' : ('unsigned int', 32),
38 'sq' : ('signed int', 64),
39 'uq' : ('unsigned int', 64),
40 'sf' : ('float', 32),
41 'df' : ('float', 64)
42}};
43
44def operands {{
45 # General Purpose Integer Reg Operands
46 'Ra': ('IntReg', 'uw', 'RA', 'IsInteger', 1),
47 'Rb': ('IntReg', 'uw', 'RB', 'IsInteger', 2),
48 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
49 'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 4),
50
51 # General Purpose Floating Point Reg Operands
52 'Fa': ('FloatReg', 'df', 'FRA', 'IsFloating', 1),
53 'Fb': ('FloatReg', 'df', 'FRB', 'IsFloating', 2),
54 'Fc': ('FloatReg', 'df', 'FRC', 'IsFloating', 3),
55 'Fs': ('FloatReg', 'df', 'FRS', 'IsFloating', 4),
56 'Ft': ('FloatReg', 'df', 'FRT', 'IsFloating', 5),
57
58 # Memory Operand
59 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
60
61 # Program counter and next
|
64
65 # Control registers
66 'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),
67 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
68 'CTR': ('IntReg', 'uw', 'INTREG_CTR', 'IsInteger', 9),
69 'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),
70
71 # Setting as IntReg so things are stored as an integer, not double
72 'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9),
73
74 # Registers for linked loads and stores
75 'Rsv': ('IntReg', 'uw', 'INTREG_RSV', 'IsInteger', 9),
76 'RsvLen': ('IntReg', 'uw', 'INTREG_RSV_LEN', 'IsInteger', 9),
77 'RsvAddr': ('IntReg', 'uw', 'INTREG_RSV_ADDR', 'IsInteger', 9),
78
79 # Hack for non-full-system syscall emulation
80 'R0': ('IntReg', 'uw', '0', None, 1),
81}};
| 63
64 # Control registers
65 'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),
66 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
67 'CTR': ('IntReg', 'uw', 'INTREG_CTR', 'IsInteger', 9),
68 'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),
69
70 # Setting as IntReg so things are stored as an integer, not double
71 'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9),
72
73 # Registers for linked loads and stores
74 'Rsv': ('IntReg', 'uw', 'INTREG_RSV', 'IsInteger', 9),
75 'RsvLen': ('IntReg', 'uw', 'INTREG_RSV_LEN', 'IsInteger', 9),
76 'RsvAddr': ('IntReg', 'uw', 'INTREG_RSV_ADDR', 'IsInteger', 9),
77
78 # Hack for non-full-system syscall emulation
79 'R0': ('IntReg', 'uw', '0', None, 1),
80}};
|