| fp.isa (6691:cd68b6ecd68d) | fp.isa (8588:ef28ed90449d) |
|---|---|
| 1// -*- mode:c++ -*- 2 3// Copyright (c) 2009 The University of Edinburgh 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 70 unchanged lines hidden (view full) --- 79 header_output += header_output_rc1 80 decoder_output += decoder_output_rc1 81 exec_output += exec_output_rc1 82}}; 83 84// Floating point elementary arithmetic operations. Besides having two 85// versions of each instruction for when Rc is set or not, we also have 86// to alter lots of special registers depending on the result of the | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2009 The University of Edinburgh 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 70 unchanged lines hidden (view full) --- 79 header_output += header_output_rc1 80 decoder_output += decoder_output_rc1 81 exec_output += exec_output_rc1 82}}; 83 84// Floating point elementary arithmetic operations. Besides having two 85// versions of each instruction for when Rc is set or not, we also have 86// to alter lots of special registers depending on the result of the |
| 87// operation. The result is always in Ft.sf. | 87// operation. The result is always in Ft_sf. |
| 88def format FloatArithOp(code, inst_flags = []) {{ 89 90 # Code when Rc is set 91 code_rc1 = code + readFPSCRCode + computeCR1Code 92 93 # Generate the first class 94 (header_output, decoder_output, decode_block, exec_output) = \ 95 GenAluOp(name, Name, 'FloatOp', code, inst_flags, --- 8 unchanged lines hidden (view full) --- 104 header_output += header_output_rc1 105 decoder_output += decoder_output_rc1 106 exec_output += exec_output_rc1 107}}; 108 109// Floating point rounding and conversion operations. Besides having two 110// versions of each instruction for when Rc is set or not, we also have 111// to alter lots of special registers depending on the result of the | 88def format FloatArithOp(code, inst_flags = []) {{ 89 90 # Code when Rc is set 91 code_rc1 = code + readFPSCRCode + computeCR1Code 92 93 # Generate the first class 94 (header_output, decoder_output, decode_block, exec_output) = \ 95 GenAluOp(name, Name, 'FloatOp', code, inst_flags, --- 8 unchanged lines hidden (view full) --- 104 header_output += header_output_rc1 105 decoder_output += decoder_output_rc1 106 exec_output += exec_output_rc1 107}}; 108 109// Floating point rounding and conversion operations. Besides having two 110// versions of each instruction for when Rc is set or not, we also have 111// to alter lots of special registers depending on the result of the |
| 112// operation. The result is always in Ft.sf. | 112// operation. The result is always in Ft_sf. |
| 113def format FloatConvertOp(code, inst_flags = []) {{ 114 115 # Code when Rc is set 116 code_rc1 = code + readFPSCRCode + computeCR1Code 117 118 # Generate the first class 119 (header_output, decoder_output, decode_block, exec_output) = \ 120 GenAluOp(name, Name, 'FloatOp', code, inst_flags, --- 12 unchanged lines hidden --- | 113def format FloatConvertOp(code, inst_flags = []) {{ 114 115 # Code when Rc is set 116 code_rc1 = code + readFPSCRCode + computeCR1Code 117 118 # Generate the first class 119 (header_output, decoder_output, decode_block, exec_output) = \ 120 GenAluOp(name, Name, 'FloatOp', code, inst_flags, --- 12 unchanged lines hidden --- |