decoder.isa (7791:762276cd3cc7) | decoder.isa (8588:ef28ed90449d) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2009 The University of Edinburgh 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 32 unchanged lines hidden (view full) --- 41 format IntImmOp { 42 10: cmpli({{ 43 Xer xer = XER; 44 uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so); 45 CR = insertCRField(CR, BF, cr); 46 }}); 47 11: cmpi({{ 48 Xer xer = XER; | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2009 The University of Edinburgh 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 32 unchanged lines hidden (view full) --- 41 format IntImmOp { 42 10: cmpli({{ 43 Xer xer = XER; 44 uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so); 45 CR = insertCRField(CR, BF, cr); 46 }}); 47 11: cmpi({{ 48 Xer xer = XER; |
49 uint32_t cr = makeCRField(Ra.sw, (int32_t)imm, xer.so); | 49 uint32_t cr = makeCRField(Ra_sw, (int32_t)imm, xer.so); |
50 CR = insertCRField(CR, BF, cr); 51 }}); 52 } 53 54 // Some instructions use bits 21 - 30, others 22 - 30. We have to use 55 // the larger size to account for all opcodes. For those that use the 56 // smaller value, the OE bit is bit 21. Therefore, we have two versions 57 // of each instruction: 1 with OE set, the other without. For an --- 25 unchanged lines hidden (view full) --- 83 computeCA = true); 84 200: subfze({{ ~Ra }}, {{ xer.ca }}, 85 computeCA = true); 86 } 87 88 // Arithmetic instructions all use source registers Ra and Rb, 89 // with destination register Rt. 90 format IntArithOp { | 50 CR = insertCRField(CR, BF, cr); 51 }}); 52 } 53 54 // Some instructions use bits 21 - 30, others 22 - 30. We have to use 55 // the larger size to account for all opcodes. For those that use the 56 // smaller value, the OE bit is bit 21. Therefore, we have two versions 57 // of each instruction: 1 with OE set, the other without. For an --- 25 unchanged lines hidden (view full) --- 83 computeCA = true); 84 200: subfze({{ ~Ra }}, {{ xer.ca }}, 85 computeCA = true); 86 } 87 88 // Arithmetic instructions all use source registers Ra and Rb, 89 // with destination register Rt. 90 format IntArithOp { |
91 75: mulhw({{ int64_t prod = Ra.sq * Rb.sq; Rt = prod >> 32; }}); 92 11: mulhwu({{ uint64_t prod = Ra.uq * Rb.uq; Rt = prod >> 32; }}); 93 235: mullw({{ int64_t prod = Ra.sq * Rb.sq; Rt = prod; }}); 94 747: mullwo({{ int64_t src1 = Ra.sq; int64_t src2 = Rb; int64_t prod = src1 * src2; Rt = prod; }}, | 91 75: mulhw({{ int64_t prod = Ra_sq * Rb_sq; Rt = prod >> 32; }}); 92 11: mulhwu({{ uint64_t prod = Ra_uq * Rb_uq; Rt = prod >> 32; }}); 93 235: mullw({{ int64_t prod = Ra_sq * Rb_sq; Rt = prod; }}); 94 747: mullwo({{ int64_t src1 = Ra_sq; int64_t src2 = Rb; int64_t prod = src1 * src2; Rt = prod; }}, |
95 true); 96 97 491: divw({{ | 95 true); 96 97 491: divw({{ |
98 int32_t src1 = Ra.sw; 99 int32_t src2 = Rb.sw; | 98 int32_t src1 = Ra_sw; 99 int32_t src2 = Rb_sw; |
100 if ((src1 != 0x80000000 || src2 != 0xffffffff) 101 && src2 != 0) { 102 Rt = src1 / src2; 103 } else { 104 Rt = 0; 105 } 106 }}); 107 108 1003: divwo({{ | 100 if ((src1 != 0x80000000 || src2 != 0xffffffff) 101 && src2 != 0) { 102 Rt = src1 / src2; 103 } else { 104 Rt = 0; 105 } 106 }}); 107 108 1003: divwo({{ |
109 int32_t src1 = Ra.sw; 110 int32_t src2 = Rb.sw; | 109 int32_t src1 = Ra_sw; 110 int32_t src2 = Rb_sw; |
111 if ((src1 != 0x80000000 || src2 != 0xffffffff) 112 && src2 != 0) { 113 Rt = src1 / src2; 114 } else { 115 Rt = 0; 116 divSetOV = true; 117 } 118 }}, 119 true); 120 121 459: divwu({{ | 111 if ((src1 != 0x80000000 || src2 != 0xffffffff) 112 && src2 != 0) { 113 Rt = src1 / src2; 114 } else { 115 Rt = 0; 116 divSetOV = true; 117 } 118 }}, 119 true); 120 121 459: divwu({{ |
122 uint32_t src1 = Ra.sw; 123 uint32_t src2 = Rb.sw; | 122 uint32_t src1 = Ra_sw; 123 uint32_t src2 = Rb_sw; |
124 if (src2 != 0) { 125 Rt = src1 / src2; 126 } else { 127 Rt = 0; 128 } 129 }}); 130 131 971: divwuo({{ | 124 if (src2 != 0) { 125 Rt = src1 / src2; 126 } else { 127 Rt = 0; 128 } 129 }}); 130 131 971: divwuo({{ |
132 uint32_t src1 = Ra.sw; 133 uint32_t src2 = Rb.sw; | 132 uint32_t src1 = Ra_sw; 133 uint32_t src2 = Rb_sw; |
134 if (src2 != 0) { 135 Rt = src1 / src2; 136 } else { 137 Rt = 0; 138 divSetOV = true; 139 } 140 }}, 141 true); --- 100 unchanged lines hidden (view full) --- 242 XER = xer1; 243 }}); 244 } 245 246 // Generic integer format instructions. 247 format IntOp { 248 0: cmp({{ 249 Xer xer = XER; | 134 if (src2 != 0) { 135 Rt = src1 / src2; 136 } else { 137 Rt = 0; 138 divSetOV = true; 139 } 140 }}, 141 true); --- 100 unchanged lines hidden (view full) --- 242 XER = xer1; 243 }}); 244 } 245 246 // Generic integer format instructions. 247 format IntOp { 248 0: cmp({{ 249 Xer xer = XER; |
250 uint32_t cr = makeCRField(Ra.sw, Rb.sw, xer.so); | 250 uint32_t cr = makeCRField(Ra_sw, Rb_sw, xer.so); |
251 CR = insertCRField(CR, BF, cr); 252 }}); 253 32: cmpl({{ 254 Xer xer = XER; 255 uint32_t cr = makeCRField(Ra, Rb, xer.so); 256 CR = insertCRField(CR, BF, cr); 257 }}); 258 144: mtcrf({{ --- 18 unchanged lines hidden (view full) --- 277 } 278 } 279 280 // All loads with an index register. The non-update versions 281 // all use the value 0 if Ra == R0, not the value contained in 282 // R0. Others update Ra with the effective address. In all cases, 283 // Ra and Rb are source registers, Rt is the destintation. 284 format LoadIndexOp { | 251 CR = insertCRField(CR, BF, cr); 252 }}); 253 32: cmpl({{ 254 Xer xer = XER; 255 uint32_t cr = makeCRField(Ra, Rb, xer.so); 256 CR = insertCRField(CR, BF, cr); 257 }}); 258 144: mtcrf({{ --- 18 unchanged lines hidden (view full) --- 277 } 278 } 279 280 // All loads with an index register. The non-update versions 281 // all use the value 0 if Ra == R0, not the value contained in 282 // R0. Others update Ra with the effective address. In all cases, 283 // Ra and Rb are source registers, Rt is the destintation. 284 format LoadIndexOp { |
285 87: lbzx({{ Rt = Mem.ub; }}); 286 279: lhzx({{ Rt = Mem.uh; }}); 287 343: lhax({{ Rt = Mem.sh; }}); | 285 87: lbzx({{ Rt = Mem_ub; }}); 286 279: lhzx({{ Rt = Mem_uh; }}); 287 343: lhax({{ Rt = Mem_sh; }}); |
288 23: lwzx({{ Rt = Mem; }}); | 288 23: lwzx({{ Rt = Mem; }}); |
289 341: lwax({{ Rt = Mem.sw; }}); 290 20: lwarx({{ Rt = Mem.sw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }}); 291 535: lfsx({{ Ft.sf = Mem.sf; }}); 292 599: lfdx({{ Ft = Mem.df; }}); 293 855: lfiwax({{ Ft.uw = Mem; }}); | 289 341: lwax({{ Rt = Mem_sw; }}); 290 20: lwarx({{ Rt = Mem_sw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }}); 291 535: lfsx({{ Ft_sf = Mem_sf; }}); 292 599: lfdx({{ Ft = Mem_df; }}); 293 855: lfiwax({{ Ft_uw = Mem; }}); |
294 } 295 296 format LoadIndexUpdateOp { | 294 } 295 296 format LoadIndexUpdateOp { |
297 119: lbzux({{ Rt = Mem.ub; }}); 298 311: lhzux({{ Rt = Mem.uh; }}); 299 375: lhaux({{ Rt = Mem.sh; }}); | 297 119: lbzux({{ Rt = Mem_ub; }}); 298 311: lhzux({{ Rt = Mem_uh; }}); 299 375: lhaux({{ Rt = Mem_sh; }}); |
300 55: lwzux({{ Rt = Mem; }}); | 300 55: lwzux({{ Rt = Mem; }}); |
301 373: lwaux({{ Rt = Mem.sw; }}); 302 567: lfsux({{ Ft.sf = Mem.sf; }}); 303 631: lfdux({{ Ft = Mem.df; }}); | 301 373: lwaux({{ Rt = Mem_sw; }}); 302 567: lfsux({{ Ft_sf = Mem_sf; }}); 303 631: lfdux({{ Ft = Mem_df; }}); |
304 } 305 306 format StoreIndexOp { | 304 } 305 306 format StoreIndexOp { |
307 215: stbx({{ Mem.ub = Rs.ub; }}); 308 407: sthx({{ Mem.uh = Rs.uh; }}); | 307 215: stbx({{ Mem_ub = Rs_ub; }}); 308 407: sthx({{ Mem_uh = Rs_uh; }}); |
309 151: stwx({{ Mem = Rs; }}); 310 150: stwcx({{ 311 bool store_performed = false; 312 if (Rsv) { 313 if (RsvLen == 4) { 314 if (RsvAddr == EA) { 315 Mem = Rs; 316 store_performed = true; 317 } 318 } 319 } 320 Xer xer = XER; 321 Cr cr = CR; 322 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so); 323 CR = cr; 324 Rsv = 0; 325 }}); | 309 151: stwx({{ Mem = Rs; }}); 310 150: stwcx({{ 311 bool store_performed = false; 312 if (Rsv) { 313 if (RsvLen == 4) { 314 if (RsvAddr == EA) { 315 Mem = Rs; 316 store_performed = true; 317 } 318 } 319 } 320 Xer xer = XER; 321 Cr cr = CR; 322 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so); 323 CR = cr; 324 Rsv = 0; 325 }}); |
326 663: stfsx({{ Mem.sf = Fs.sf; }}); 327 727: stfdx({{ Mem.df = Fs; }}); 328 983: stfiwx({{ Mem = Fs.uw; }}); | 326 663: stfsx({{ Mem_sf = Fs_sf; }}); 327 727: stfdx({{ Mem_df = Fs; }}); 328 983: stfiwx({{ Mem = Fs_uw; }}); |
329 } 330 331 format StoreIndexUpdateOp { | 329 } 330 331 format StoreIndexUpdateOp { |
332 247: stbux({{ Mem.ub = Rs.ub; }}); 333 439: sthux({{ Mem.uh = Rs.uh; }}); | 332 247: stbux({{ Mem_ub = Rs_ub; }}); 333 439: sthux({{ Mem_uh = Rs_uh; }}); |
334 183: stwux({{ Mem = Rs; }}); | 334 183: stwux({{ Mem = Rs; }}); |
335 695: stfsux({{ Mem.sf = Fs.sf; }}); 336 759: stfdux({{ Mem.df = Fs; }}); | 335 695: stfsux({{ Mem_sf = Fs_sf; }}); 336 759: stfdux({{ Mem_df = Fs; }}); |
337 } 338 339 // These instructions all provide data cache hints 340 format MiscOp { 341 278: dcbt({{ }}); 342 246: dcbtst({{ }}); 343 598: sync({{ }}, [ IsMemBarrier ]); 344 854: eieio({{ }}, [ IsMemBarrier ]); --- 10 unchanged lines hidden (view full) --- 355 format IntImmArithOp { 356 12: addic({{ uint32_t src = Ra; Rt = src + imm; }}, 357 [computeCA]); 358 13: addic_({{ uint32_t src = Ra; Rt = src + imm; }}, 359 [computeCA, computeCR0]); 360 8: subfic({{ int32_t src = ~Ra; Rt = src + imm + 1; }}, 361 [computeCA]); 362 7: mulli({{ | 337 } 338 339 // These instructions all provide data cache hints 340 format MiscOp { 341 278: dcbt({{ }}); 342 246: dcbtst({{ }}); 343 598: sync({{ }}, [ IsMemBarrier ]); 344 854: eieio({{ }}, [ IsMemBarrier ]); --- 10 unchanged lines hidden (view full) --- 355 format IntImmArithOp { 356 12: addic({{ uint32_t src = Ra; Rt = src + imm; }}, 357 [computeCA]); 358 13: addic_({{ uint32_t src = Ra; Rt = src + imm; }}, 359 [computeCA, computeCR0]); 360 8: subfic({{ int32_t src = ~Ra; Rt = src + imm + 1; }}, 361 [computeCA]); 362 7: mulli({{ |
363 int32_t src = Ra.sw; | 363 int32_t src = Ra_sw; |
364 int64_t prod = src * imm; 365 Rt = (uint32_t)prod; 366 }}); 367 } 368 369 format IntImmLogicOp { 370 24: ori({{ Ra = Rs | uimm; }}); 371 25: oris({{ Ra = Rs | (uimm << 16); }}); --- 99 unchanged lines hidden (view full) --- 471 472 format IntRotateOp { 473 21: rlwinm({{ Ra = rotateValue(Rs, sh) & fullMask; }}); 474 23: rlwnm({{ Ra = rotateValue(Rs, Rb) & fullMask; }}); 475 20: rlwimi({{ Ra = (rotateValue(Rs, sh) & fullMask) | (Ra & ~fullMask); }}); 476 } 477 478 format LoadDispOp { | 364 int64_t prod = src * imm; 365 Rt = (uint32_t)prod; 366 }}); 367 } 368 369 format IntImmLogicOp { 370 24: ori({{ Ra = Rs | uimm; }}); 371 25: oris({{ Ra = Rs | (uimm << 16); }}); --- 99 unchanged lines hidden (view full) --- 471 472 format IntRotateOp { 473 21: rlwinm({{ Ra = rotateValue(Rs, sh) & fullMask; }}); 474 23: rlwnm({{ Ra = rotateValue(Rs, Rb) & fullMask; }}); 475 20: rlwimi({{ Ra = (rotateValue(Rs, sh) & fullMask) | (Ra & ~fullMask); }}); 476 } 477 478 format LoadDispOp { |
479 34: lbz({{ Rt = Mem.ub; }}); 480 40: lhz({{ Rt = Mem.uh; }}); 481 42: lha({{ Rt = Mem.sh; }}); | 479 34: lbz({{ Rt = Mem_ub; }}); 480 40: lhz({{ Rt = Mem_uh; }}); 481 42: lha({{ Rt = Mem_sh; }}); |
482 32: lwz({{ Rt = Mem; }}); | 482 32: lwz({{ Rt = Mem; }}); |
483 58: lwa({{ Rt = Mem.sw; }}, | 483 58: lwa({{ Rt = Mem_sw; }}, |
484 {{ EA = Ra + (disp & 0xfffffffc); }}, 485 {{ EA = disp & 0xfffffffc; }}); | 484 {{ EA = Ra + (disp & 0xfffffffc); }}, 485 {{ EA = disp & 0xfffffffc; }}); |
486 48: lfs({{ Ft.sf = Mem.sf; }}); 487 50: lfd({{ Ft = Mem.df; }}); | 486 48: lfs({{ Ft_sf = Mem_sf; }}); 487 50: lfd({{ Ft = Mem_df; }}); |
488 } 489 490 format LoadDispUpdateOp { | 488 } 489 490 format LoadDispUpdateOp { |
491 35: lbzu({{ Rt = Mem.ub; }}); 492 41: lhzu({{ Rt = Mem.uh; }}); 493 43: lhau({{ Rt = Mem.sh; }}); | 491 35: lbzu({{ Rt = Mem_ub; }}); 492 41: lhzu({{ Rt = Mem_uh; }}); 493 43: lhau({{ Rt = Mem_sh; }}); |
494 33: lwzu({{ Rt = Mem; }}); | 494 33: lwzu({{ Rt = Mem; }}); |
495 49: lfsu({{ Ft.sf = Mem.sf; }}); 496 51: lfdu({{ Ft = Mem.df; }}); | 495 49: lfsu({{ Ft_sf = Mem_sf; }}); 496 51: lfdu({{ Ft = Mem_df; }}); |
497 } 498 499 format StoreDispOp { | 497 } 498 499 format StoreDispOp { |
500 38: stb({{ Mem.ub = Rs.ub; }}); 501 44: sth({{ Mem.uh = Rs.uh; }}); | 500 38: stb({{ Mem_ub = Rs_ub; }}); 501 44: sth({{ Mem_uh = Rs_uh; }}); |
502 36: stw({{ Mem = Rs; }}); | 502 36: stw({{ Mem = Rs; }}); |
503 52: stfs({{ Mem.sf = Fs.sf; }}); 504 54: stfd({{ Mem.df = Fs; }}); | 503 52: stfs({{ Mem_sf = Fs_sf; }}); 504 54: stfd({{ Mem_df = Fs; }}); |
505 } 506 507 format StoreDispUpdateOp { | 505 } 506 507 format StoreDispUpdateOp { |
508 39: stbu({{ Mem.ub = Rs.ub; }}); 509 45: sthu({{ Mem.uh = Rs.uh; }}); | 508 39: stbu({{ Mem_ub = Rs_ub; }}); 509 45: sthu({{ Mem_uh = Rs_uh; }}); |
510 37: stwu({{ Mem = Rs; }}); | 510 37: stwu({{ Mem = Rs; }}); |
511 53: stfsu({{ Mem.sf = Fs.sf; }}); 512 55: stfdu({{ Mem.df = Fs; }}); | 511 53: stfsu({{ Mem_sf = Fs_sf; }}); 512 55: stfdu({{ Mem_df = Fs; }}); |
513 } 514 515 17: IntOp::sc({{ xc->syscall(R0); }}, 516 [ IsSyscall, IsNonSpeculative, IsSerializeAfter ]); 517 518 format FloatArithOp { 519 59: decode A_XO { 520 21: fadds({{ Ft = Fa + Fb; }}); --- 16 unchanged lines hidden (view full) --- 537 29: fmadd({{ Ft = (Fa * Fc) + Fb; }}); 538 28: fmsub({{ Ft = (Fa * Fc) - Fb; }}); 539 31: fnmadd({{ Ft = -((Fa * Fc) + Fb); }}); 540 30: fnmsub({{ Ft = -((Fa * Fc) - Fb); }}); 541 } 542 543 default: decode XO_XO { 544 format FloatConvertOp { | 513 } 514 515 17: IntOp::sc({{ xc->syscall(R0); }}, 516 [ IsSyscall, IsNonSpeculative, IsSerializeAfter ]); 517 518 format FloatArithOp { 519 59: decode A_XO { 520 21: fadds({{ Ft = Fa + Fb; }}); --- 16 unchanged lines hidden (view full) --- 537 29: fmadd({{ Ft = (Fa * Fc) + Fb; }}); 538 28: fmsub({{ Ft = (Fa * Fc) - Fb; }}); 539 31: fnmadd({{ Ft = -((Fa * Fc) + Fb); }}); 540 30: fnmsub({{ Ft = -((Fa * Fc) - Fb); }}); 541 } 542 543 default: decode XO_XO { 544 format FloatConvertOp { |
545 12: frsp({{ Ft.sf = Fb; }}); 546 15: fctiwz({{ Ft.sw = (int32_t)trunc(Fb); }}); | 545 12: frsp({{ Ft_sf = Fb; }}); 546 15: fctiwz({{ Ft_sw = (int32_t)trunc(Fb); }}); |
547 } 548 549 format FloatOp { 550 0: fcmpu({{ 551 uint32_t c = makeCRField(Fa, Fb); 552 Fpscr fpscr = FPSCR; 553 fpscr.fprf.fpcc = c; 554 FPSCR = fpscr; 555 CR = insertCRField(CR, BF, c); 556 }}); 557 } 558 559 format FloatRCCheckOp { 560 72: fmr({{ Ft = Fb; }}); 561 264: fabs({{ | 547 } 548 549 format FloatOp { 550 0: fcmpu({{ 551 uint32_t c = makeCRField(Fa, Fb); 552 Fpscr fpscr = FPSCR; 553 fpscr.fprf.fpcc = c; 554 FPSCR = fpscr; 555 CR = insertCRField(CR, BF, c); 556 }}); 557 } 558 559 format FloatRCCheckOp { 560 72: fmr({{ Ft = Fb; }}); 561 264: fabs({{ |
562 Ft.uq = Fb.uq; 563 Ft.uq = insertBits(Ft.uq, 63, 0); }}); | 562 Ft_uq = Fb_uq; 563 Ft_uq = insertBits(Ft_uq, 63, 0); }}); |
564 136: fnabs({{ | 564 136: fnabs({{ |
565 Ft.uq = Fb.uq; 566 Ft.uq = insertBits(Ft.uq, 63, 1); }}); | 565 Ft_uq = Fb_uq; 566 Ft_uq = insertBits(Ft_uq, 63, 1); }}); |
567 40: fneg({{ Ft = -Fb; }}); 568 8: fcpsgn({{ | 567 40: fneg({{ Ft = -Fb; }}); 568 8: fcpsgn({{ |
569 Ft.uq = Fb.uq; 570 Ft.uq = insertBits(Ft.uq, 63, Fa.uq<63:63>); | 569 Ft_uq = Fb_uq; 570 Ft_uq = insertBits(Ft_uq, 63, Fa_uq<63:63>); |
571 }}); | 571 }}); |
572 583: mffs({{ Ft.uq = FPSCR; }}); | 572 583: mffs({{ Ft_uq = FPSCR; }}); |
573 134: mtfsfi({{ 574 FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W)), U_FIELD); 575 }}); 576 711: mtfsf({{ | 573 134: mtfsfi({{ 574 FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W)), U_FIELD); 575 }}); 576 711: mtfsf({{ |
577 if (L == 1) { FPSCR = Fb.uq; } | 577 if (L == 1) { FPSCR = Fb_uq; } |
578 else { 579 for (int i = 0; i < 8; ++i) { 580 if (bits(FLM, i) == 1) { 581 int k = 4 * (i + (8 * (1 - W))); 582 FPSCR = insertBits(FPSCR, k, k + 3, | 578 else { 579 for (int i = 0; i < 8; ++i) { 580 if (bits(FLM, i) == 1) { 581 int k = 4 * (i + (8 * (1 - W))); 582 FPSCR = insertBits(FPSCR, k, k + 3, |
583 bits(Fb.uq, k, k + 3)); | 583 bits(Fb_uq, k, k + 3)); |
584 } 585 } 586 } 587 }}); 588 70: mtfsb0({{ FPSCR = insertBits(FPSCR, 31 - BT, 0); }}); 589 38: mtfsb1({{ FPSCR = insertBits(FPSCR, 31 - BT, 1); }}); 590 } 591 } 592 } 593} | 584 } 585 } 586 } 587 }}); 588 70: mtfsb0({{ FPSCR = insertBits(FPSCR, 31 - BT, 0); }}); 589 38: mtfsb1({{ FPSCR = insertBits(FPSCR, 31 - BT, 1); }}); 590 } 591 } 592 } 593} |