decoder.isa (6691:cd68b6ecd68d) | decoder.isa (7720:65d338a8dba4) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2009 The University of Edinburgh 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 367 unchanged lines hidden (view full) --- 376 29: andis_({{ Ra = Rs & (uimm << 16); }}, 377 true); 378 } 379 380 16: decode AA { 381 382 // Conditionally branch relative to PC based on CR and CTR. 383 format BranchPCRelCondCtr { | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2009 The University of Edinburgh 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 367 unchanged lines hidden (view full) --- 376 29: andis_({{ Ra = Rs & (uimm << 16); }}, 377 true); 378 } 379 380 16: decode AA { 381 382 // Conditionally branch relative to PC based on CR and CTR. 383 format BranchPCRelCondCtr { |
384 0: bc({{ NPC = PC + disp; }}); | 384 0: bc({{ 385 PowerISA::PCState pc = PCS; 386 pc.npc((uint32_t)(pc.pc() + disp)); 387 PCS = pc; 388 }}); |
385 } 386 387 // Conditionally branch to fixed address based on CR and CTR. 388 format BranchNonPCRelCondCtr { | 389 } 390 391 // Conditionally branch to fixed address based on CR and CTR. 392 format BranchNonPCRelCondCtr { |
389 1: bca({{ NPC = targetAddr; }}); | 393 1: bca({{ 394 PowerISA::PCState pc = PCS; 395 pc.npc(targetAddr); 396 PCS = pc; 397 }}); |
390 } 391 } 392 393 18: decode AA { 394 395 // Unconditionally branch relative to PC. 396 format BranchPCRel { | 398 } 399 } 400 401 18: decode AA { 402 403 // Unconditionally branch relative to PC. 404 format BranchPCRel { |
397 0: b({{ NPC = PC + disp; }}); | 405 0: b({{ 406 PowerISA::PCState pc = PCS; 407 pc.npc((uint32_t)(pc.pc() + disp)); 408 PCS = pc; 409 }}); |
398 } 399 400 // Unconditionally branch to fixed address. 401 format BranchNonPCRel { | 410 } 411 412 // Unconditionally branch to fixed address. 413 format BranchNonPCRel { |
402 1: ba({{ NPC = targetAddr; }}); | 414 1: ba({{ 415 PowerISA::PCState pc = PCS; 416 pc.npc(targetAddr); 417 PCS = pc; 418 }}); |
403 } 404 } 405 406 19: decode XO_XO { 407 408 // Conditionally branch to address in LR based on CR and CTR. 409 format BranchLrCondCtr { | 419 } 420 } 421 422 19: decode XO_XO { 423 424 // Conditionally branch to address in LR based on CR and CTR. 425 format BranchLrCondCtr { |
410 16: bclr({{ NPC = LR & 0xfffffffc; }}); | 426 16: bclr({{ 427 PowerISA::PCState pc = PCS; 428 pc.npc(LR & 0xfffffffc); 429 PCS = pc; 430 }}); |
411 } 412 413 // Conditionally branch to address in CTR based on CR. 414 format BranchCtrCond { | 431 } 432 433 // Conditionally branch to address in CTR based on CR. 434 format BranchCtrCond { |
415 528: bcctr({{ NPC = CTR & 0xfffffffc; }}); | 435 528: bcctr({{ 436 PowerISA::PCState pc = PCS; 437 pc.npc(CTR & 0xfffffffc); 438 PCS = pc; 439 }}); |
416 } 417 418 // Condition register manipulation instructions. 419 format CondLogicOp { 420 257: crand({{ 421 uint32_t crBa = bits(CR, 31 - ba); 422 uint32_t crBb = bits(CR, 31 - bb); 423 CR = insertBits(CR, 31 - bt, crBa & crBb); --- 170 unchanged lines hidden --- | 440 } 441 442 // Condition register manipulation instructions. 443 format CondLogicOp { 444 257: crand({{ 445 uint32_t crBa = bits(CR, 31 - ba); 446 uint32_t crBb = bits(CR, 31 - bb); 447 CR = insertBits(CR, 31 - bt, crBa & crBb); --- 170 unchanged lines hidden --- |