decoder.isa (13800:cffc4c0fc94e) decoder.isa (13801:e18de9c80ce3)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2009 The University of Edinburgh
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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381 29: andis_({{ Ra = Rs & (uimm << 16); }},
382 true);
383 }
384
385 16: decode AA {
386
387 // Conditionally branch relative to PC based on CR and CTR.
388 format BranchPCRelCondCtr {
1// -*- mode:c++ -*-
2
3// Copyright (c) 2009 The University of Edinburgh
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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381 29: andis_({{ Ra = Rs & (uimm << 16); }},
382 true);
383 }
384
385 16: decode AA {
386
387 // Conditionally branch relative to PC based on CR and CTR.
388 format BranchPCRelCondCtr {
389 0: bc({{ NPC = (uint32_t)(PC + disp); }});
389 0: bc({{ NIA = (uint32_t)(CIA + disp); }});
390 }
391
392 // Conditionally branch to fixed address based on CR and CTR.
393 format BranchNonPCRelCondCtr {
390 }
391
392 // Conditionally branch to fixed address based on CR and CTR.
393 format BranchNonPCRelCondCtr {
394 1: bca({{ NPC = targetAddr; }});
394 1: bca({{ NIA = targetAddr; }});
395 }
396 }
397
398 18: decode AA {
399
400 // Unconditionally branch relative to PC.
401 format BranchPCRel {
395 }
396 }
397
398 18: decode AA {
399
400 // Unconditionally branch relative to PC.
401 format BranchPCRel {
402 0: b({{ NPC = (uint32_t)(PC + disp); }});
402 0: b({{ NIA = (uint32_t)(CIA + disp); }});
403 }
404
405 // Unconditionally branch to fixed address.
406 format BranchNonPCRel {
403 }
404
405 // Unconditionally branch to fixed address.
406 format BranchNonPCRel {
407 1: ba({{ NPC = targetAddr; }});
407 1: ba({{ NIA = targetAddr; }});
408 }
409 }
410
411 19: decode XO_XO {
412
413 // Conditionally branch to address in LR based on CR and CTR.
414 format BranchLrCondCtr {
408 }
409 }
410
411 19: decode XO_XO {
412
413 // Conditionally branch to address in LR based on CR and CTR.
414 format BranchLrCondCtr {
415 16: bclr({{ NPC = LR & 0xfffffffc; }});
415 16: bclr({{ NIA = LR & 0xfffffffc; }});
416 }
417
418 // Conditionally branch to address in CTR based on CR.
419 format BranchCtrCond {
416 }
417
418 // Conditionally branch to address in CTR based on CR.
419 format BranchCtrCond {
420 528: bcctr({{ NPC = CTR & 0xfffffffc; }});
420 528: bcctr({{ NIA = CTR & 0xfffffffc; }});
421 }
422
423 // Condition register manipulation instructions.
424 format CondLogicOp {
425 257: crand({{
426 uint32_t crBa = bits(CR, 31 - ba);
427 uint32_t crBb = bits(CR, 31 - bb);
428 CR = insertBits(CR, 31 - bt, crBa & crBb);

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422
423 // Condition register manipulation instructions.
424 format CondLogicOp {
425 257: crand({{
426 uint32_t crBa = bits(CR, 31 - ba);
427 uint32_t crBb = bits(CR, 31 - bb);
428 CR = insertBits(CR, 31 - bt, crBa & crBb);

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