decoder.isa (12692:1eaaa1d75080) | decoder.isa (13800:cffc4c0fc94e) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2009 The University of Edinburgh 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 74 unchanged lines hidden (view full) --- 83 computeCA = true); 84 200: subfze({{ ~Ra }}, {{ xer.ca }}, 85 computeCA = true); 86 } 87 88 // Arithmetic instructions all use source registers Ra and Rb, 89 // with destination register Rt. 90 format IntArithOp { | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2009 The University of Edinburgh 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 74 unchanged lines hidden (view full) --- 83 computeCA = true); 84 200: subfze({{ ~Ra }}, {{ xer.ca }}, 85 computeCA = true); 86 } 87 88 // Arithmetic instructions all use source registers Ra and Rb, 89 // with destination register Rt. 90 format IntArithOp { |
91 75: mulhw({{ int64_t prod = Ra_sq * Rb_sq; Rt = prod >> 32; }}); 92 11: mulhwu({{ uint64_t prod = Ra_uq * Rb_uq; Rt = prod >> 32; }}); 93 235: mullw({{ int64_t prod = Ra_sq * Rb_sq; Rt = prod; }}); 94 747: mullwo({{ int64_t src1 = Ra_sq; int64_t src2 = Rb; int64_t prod = src1 * src2; Rt = prod; }}, 95 true); | 91 75: mulhw({{ int64_t prod = Ra_sd * Rb_sd; Rt = prod >> 32; }}); 92 11: mulhwu({{ uint64_t prod = Ra_ud * Rb_ud; Rt = prod >> 32; }}); 93 235: mullw({{ int64_t prod = Ra_sd * Rb_sd; Rt = prod; }}); 94 747: mullwo({{ 95 int64_t src1 = Ra_sd; 96 int64_t src2 = Rb; 97 int64_t prod = src1 * src2; 98 Rt = prod; 99 }}, 100 true); |
96 97 491: divw({{ 98 int32_t src1 = Ra_sw; 99 int32_t src2 = Rb_sw; 100 if ((src1 != 0x80000000 || src2 != 0xffffffff) 101 && src2 != 0) { 102 Rt = src1 / src2; 103 } else { --- 450 unchanged lines hidden (view full) --- 554 FPSCR = fpscr; 555 CR = insertCRField(CR, BF, c); 556 }}); 557 } 558 559 format FloatRCCheckOp { 560 72: fmr({{ Ft = Fb; }}); 561 264: fabs({{ | 101 102 491: divw({{ 103 int32_t src1 = Ra_sw; 104 int32_t src2 = Rb_sw; 105 if ((src1 != 0x80000000 || src2 != 0xffffffff) 106 && src2 != 0) { 107 Rt = src1 / src2; 108 } else { --- 450 unchanged lines hidden (view full) --- 559 FPSCR = fpscr; 560 CR = insertCRField(CR, BF, c); 561 }}); 562 } 563 564 format FloatRCCheckOp { 565 72: fmr({{ Ft = Fb; }}); 566 264: fabs({{ |
562 Ft_uq = Fb_uq; 563 Ft_uq = insertBits(Ft_uq, 63, 0); }}); | 567 Ft_ud = Fb_ud; 568 Ft_ud = insertBits(Ft_ud, 63, 0); }}); |
564 136: fnabs({{ | 569 136: fnabs({{ |
565 Ft_uq = Fb_uq; 566 Ft_uq = insertBits(Ft_uq, 63, 1); }}); | 570 Ft_ud = Fb_ud; 571 Ft_ud = insertBits(Ft_ud, 63, 1); }}); |
567 40: fneg({{ Ft = -Fb; }}); 568 8: fcpsgn({{ | 572 40: fneg({{ Ft = -Fb; }}); 573 8: fcpsgn({{ |
569 Ft_uq = Fb_uq; 570 Ft_uq = insertBits(Ft_uq, 63, Fa_uq<63:63>); | 574 Ft_ud = Fb_ud; 575 Ft_ud = insertBits(Ft_ud, 63, Fa_ud<63:63>); |
571 }}); | 576 }}); |
572 583: mffs({{ Ft_uq = FPSCR; }}); | 577 583: mffs({{ Ft_ud = FPSCR; }}); |
573 134: mtfsfi({{ 574 FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W_FIELD)), 575 U_FIELD); 576 }}); 577 711: mtfsf({{ | 578 134: mtfsfi({{ 579 FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W_FIELD)), 580 U_FIELD); 581 }}); 582 711: mtfsf({{ |
578 if (L_FIELD == 1) { FPSCR = Fb_uq; } | 583 if (L_FIELD == 1) { FPSCR = Fb_ud; } |
579 else { 580 for (int i = 0; i < 8; ++i) { 581 if (bits(FLM, i) == 1) { 582 int k = 4 * (i + (8 * (1 - W_FIELD))); 583 FPSCR = insertBits(FPSCR, k + 3, k, | 584 else { 585 for (int i = 0; i < 8; ++i) { 586 if (bits(FLM, i) == 1) { 587 int k = 4 * (i + (8 * (1 - W_FIELD))); 588 FPSCR = insertBits(FPSCR, k + 3, k, |
584 bits(Fb_uq, k + 3, k)); | 589 bits(Fb_ud, k + 3, k)); |
585 } 586 } 587 } 588 }}); 589 70: mtfsb0({{ FPSCR = insertBits(FPSCR, 31 - BT, 0); }}); 590 38: mtfsb1({{ FPSCR = insertBits(FPSCR, 31 - BT, 1); }}); 591 } 592 } 593 } 594} | 590 } 591 } 592 } 593 }}); 594 70: mtfsb0({{ FPSCR = insertBits(FPSCR, 31 - BT, 0); }}); 595 38: mtfsb1({{ FPSCR = insertBits(FPSCR, 31 - BT, 1); }}); 596 } 597 } 598 } 599} |