1// -*- mode:c++ -*- 2 3// Copyright (c) 2009 The University of Edinburgh 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 372 unchanged lines hidden (view full) --- 381 29: andis_({{ Ra = Rs & (uimm << 16); }}, 382 true); 383 } 384 385 16: decode AA { 386 387 // Conditionally branch relative to PC based on CR and CTR. 388 format BranchPCRelCondCtr { |
389 0: bc({{ NIA = (uint32_t)(CIA + disp); }}); |
390 } 391 392 // Conditionally branch to fixed address based on CR and CTR. 393 format BranchNonPCRelCondCtr { |
394 1: bca({{ NIA = targetAddr; }}); |
395 } 396 } 397 398 18: decode AA { 399 400 // Unconditionally branch relative to PC. 401 format BranchPCRel { |
402 0: b({{ NIA = (uint32_t)(CIA + disp); }}); |
403 } 404 405 // Unconditionally branch to fixed address. 406 format BranchNonPCRel { |
407 1: ba({{ NIA = targetAddr; }}); |
408 } 409 } 410 411 19: decode XO_XO { 412 413 // Conditionally branch to address in LR based on CR and CTR. 414 format BranchLrCondCtr { |
415 16: bclr({{ NIA = LR & 0xfffffffc; }}); |
416 } 417 418 // Conditionally branch to address in CTR based on CR. 419 format BranchCtrCond { |
420 528: bcctr({{ NIA = CTR & 0xfffffffc; }}); |
421 } 422 423 // Condition register manipulation instructions. 424 format CondLogicOp { 425 257: crand({{ 426 uint32_t crBa = bits(CR, 31 - ba); 427 uint32_t crBb = bits(CR, 31 - bb); 428 CR = insertBits(CR, 31 - bt, crBa & crBb); --- 171 unchanged lines hidden --- |