1// -*- mode:c++ -*-
2
3// Copyright (c) 2009 The University of Edinburgh
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Timothy M. Jones
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual Power ISA decoder
34// ------------------------------
35//
36// I've used the Power ISA Book I v2.06 for instruction formats,
37// opcode numbers, register names, etc.
38//
39decode OPCODE default Unknown::unknown() {
40
41 format IntImmOp {
42 10: cmpli({{
43 Xer xer = XER;
44 uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so);
45 CR = insertCRField(CR, BF, cr);
46 }});
47 11: cmpi({{
48 Xer xer = XER;
49 uint32_t cr = makeCRField(Ra_sw, (int32_t)imm, xer.so);
50 CR = insertCRField(CR, BF, cr);
51 }});
52 }
53
54 // Some instructions use bits 21 - 30, others 22 - 30. We have to use
55 // the larger size to account for all opcodes. For those that use the
56 // smaller value, the OE bit is bit 21. Therefore, we have two versions
57 // of each instruction: 1 with OE set, the other without. For an
58 // example see 'add' and 'addo'.
59 31: decode XO_XO {
60
61 // These instructions can all be reduced to the form
62 // Rt = src1 + src2 [+ CA], therefore we just give src1 and src2
63 // (and, if necessary, CA) definitions and let the python script
64 // deal with setting things up correctly. We also give flags to
65 // say which control registers to set.
66 format IntSumOp {
67 266: add({{ Ra }}, {{ Rb }});
68 40: subf({{ ~Ra }}, {{ Rb }}, {{ 1 }});
69 10: addc({{ Ra }}, {{ Rb }},
70 computeCA = true);
71 8: subfc({{ ~Ra }}, {{ Rb }}, {{ 1 }},
72 true);
73 104: neg({{ ~Ra }}, {{ 1 }});
74 138: adde({{ Ra }}, {{ Rb }}, {{ xer.ca }},
75 true);
76 234: addme({{ Ra }}, {{ (uint32_t)-1 }}, {{ xer.ca }},
77 true);
78 136: subfe({{ ~Ra }}, {{ Rb }}, {{ xer.ca }},
79 true);
80 232: subfme({{ ~Ra }}, {{ (uint32_t)-1 }}, {{ xer.ca }},
81 true);
82 202: addze({{ Ra }}, {{ xer.ca }},
83 computeCA = true);
84 200: subfze({{ ~Ra }}, {{ xer.ca }},
85 computeCA = true);
86 }
87
88 // Arithmetic instructions all use source registers Ra and Rb,
89 // with destination register Rt.
90 format IntArithOp {
91 75: mulhw({{ int64_t prod = Ra_sq * Rb_sq; Rt = prod >> 32; }});
92 11: mulhwu({{ uint64_t prod = Ra_uq * Rb_uq; Rt = prod >> 32; }});
93 235: mullw({{ int64_t prod = Ra_sq * Rb_sq; Rt = prod; }});
94 747: mullwo({{ int64_t src1 = Ra_sq; int64_t src2 = Rb; int64_t prod = src1 * src2; Rt = prod; }},
95 true);
96
97 491: divw({{
98 int32_t src1 = Ra_sw;
99 int32_t src2 = Rb_sw;
100 if ((src1 != 0x80000000 || src2 != 0xffffffff)
101 && src2 != 0) {
102 Rt = src1 / src2;
103 } else {
104 Rt = 0;
105 }
106 }});
107
108 1003: divwo({{
109 int32_t src1 = Ra_sw;
110 int32_t src2 = Rb_sw;
111 if ((src1 != 0x80000000 || src2 != 0xffffffff)
112 && src2 != 0) {
113 Rt = src1 / src2;
114 } else {
115 Rt = 0;
116 divSetOV = true;
117 }
118 }},
119 true);
120
121 459: divwu({{
122 uint32_t src1 = Ra_sw;
123 uint32_t src2 = Rb_sw;
124 if (src2 != 0) {
125 Rt = src1 / src2;
126 } else {
127 Rt = 0;
128 }
129 }});
130
131 971: divwuo({{
132 uint32_t src1 = Ra_sw;
133 uint32_t src2 = Rb_sw;
134 if (src2 != 0) {
135 Rt = src1 / src2;
136 } else {
137 Rt = 0;
138 divSetOV = true;
139 }
140 }},
141 true);
142 }
143
144 // Integer logic instructions use source registers Rs and Rb,
145 // with destination register Ra.
146 format IntLogicOp {
147 28: and({{ Ra = Rs & Rb; }});
148 316: xor({{ Ra = Rs ^ Rb; }});
149 476: nand({{ Ra = ~(Rs & Rb); }});
150 444: or({{ Ra = Rs | Rb; }});
151 124: nor({{ Ra = ~(Rs | Rb); }});
152 60: andc({{ Ra = Rs & ~Rb; }});
153 954: extsb({{ Ra = sext<8>(Rs); }});
154 284: eqv({{ Ra = ~(Rs ^ Rb); }});
155 412: orc({{ Ra = Rs | ~Rb; }});
156 922: extsh({{ Ra = sext<16>(Rs); }});
157 26: cntlzw({{ Ra = Rs == 0 ? 32 : 31 - findMsbSet(Rs); }});
158 508: cmpb({{
159 uint32_t val = 0;
160 for (int n = 0; n < 32; n += 8) {
161 if(bits(Rs, n, n+7) == bits(Rb, n, n+7)) {
162 val = insertBits(val, n, n+7, 0xff);
163 }
164 }
165 Ra = val;
166 }});
167
168 24: slw({{
169 if (Rb & 0x20) {
170 Ra = 0;
171 } else {
172 Ra = Rs << (Rb & 0x1f);
173 }
174 }});
175
176 536: srw({{
177 if (Rb & 0x20) {
178 Ra = 0;
179 } else {
180 Ra = Rs >> (Rb & 0x1f);
181 }
182 }});
183
184 792: sraw({{
185 bool shiftSetCA = false;
186 int32_t s = Rs;
187 if (Rb == 0) {
188 Ra = Rs;
189 shiftSetCA = true;
190 } else if (Rb & 0x20) {
191 if (s < 0) {
192 Ra = (uint32_t)-1;
193 if (s & 0x7fffffff) {
194 shiftSetCA = true;
195 } else {
196 shiftSetCA = false;
197 }
198 } else {
199 Ra = 0;
200 shiftSetCA = false;
201 }
202 } else {
203 Ra = s >> (Rb & 0x1f);
204 if (s < 0 && (s << (32 - (Rb & 0x1f))) != 0) {
205 shiftSetCA = true;
206 } else {
207 shiftSetCA = false;
208 }
209 }
210 Xer xer1 = XER;
211 if (shiftSetCA) {
212 xer1.ca = 1;
213 } else {
214 xer1.ca = 0;
215 }
216 XER = xer1;
217 }});
218 }
219
220 // Integer logic instructions with a shift value.
221 format IntShiftOp {
222 824: srawi({{
223 bool shiftSetCA = false;
224 if (sh == 0) {
225 Ra = Rs;
226 shiftSetCA = false;
227 } else {
228 int32_t s = Rs;
229 Ra = s >> sh;
230 if (s < 0 && (s << (32 - sh)) != 0) {
231 shiftSetCA = true;
232 } else {
233 shiftSetCA = false;
234 }
235 }
236 Xer xer1 = XER;
237 if (shiftSetCA) {
238 xer1.ca = 1;
239 } else {
240 xer1.ca = 0;
241 }
242 XER = xer1;
243 }});
244 }
245
246 // Generic integer format instructions.
247 format IntOp {
248 0: cmp({{
249 Xer xer = XER;
250 uint32_t cr = makeCRField(Ra_sw, Rb_sw, xer.so);
251 CR = insertCRField(CR, BF, cr);
252 }});
253 32: cmpl({{
254 Xer xer = XER;
255 uint32_t cr = makeCRField(Ra, Rb, xer.so);
256 CR = insertCRField(CR, BF, cr);
257 }});
258 144: mtcrf({{
259 uint32_t mask = 0;
260 for (int i = 0; i < 8; ++i) {
261 if (((FXM >> i) & 0x1) == 0x1) {
262 mask |= 0xf << (4 * i);
263 }
264 }
265 CR = (Rs & mask) | (CR & ~mask);
266 }});
267 19: mfcr({{ Rt = CR; }});
268 339: decode SPR {
269 0x20: mfxer({{ Rt = XER; }});
270 0x100: mflr({{ Rt = LR; }});
271 0x120: mfctr({{ Rt = CTR; }});
272 }
273 467: decode SPR {
274 0x20: mtxer({{ XER = Rs; }});
275 0x100: mtlr({{ LR = Rs; }});
276 0x120: mtctr({{ CTR = Rs; }});
277 }
278 }
279
280 // All loads with an index register. The non-update versions
281 // all use the value 0 if Ra == R0, not the value contained in
282 // R0. Others update Ra with the effective address. In all cases,
283 // Ra and Rb are source registers, Rt is the destintation.
284 format LoadIndexOp {
285 87: lbzx({{ Rt = Mem_ub; }});
286 279: lhzx({{ Rt = Mem_uh; }});
287 343: lhax({{ Rt = Mem_sh; }});
288 23: lwzx({{ Rt = Mem; }});
289 341: lwax({{ Rt = Mem_sw; }});
290 20: lwarx({{ Rt = Mem_sw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
291 535: lfsx({{ Ft_sf = Mem_sf; }});
292 599: lfdx({{ Ft = Mem_df; }});
293 855: lfiwax({{ Ft_uw = Mem; }});
294 }
295
296 format LoadIndexUpdateOp {
297 119: lbzux({{ Rt = Mem_ub; }});
298 311: lhzux({{ Rt = Mem_uh; }});
299 375: lhaux({{ Rt = Mem_sh; }});
300 55: lwzux({{ Rt = Mem; }});
301 373: lwaux({{ Rt = Mem_sw; }});
302 567: lfsux({{ Ft_sf = Mem_sf; }});
303 631: lfdux({{ Ft = Mem_df; }});
304 }
305
306 format StoreIndexOp {
307 215: stbx({{ Mem_ub = Rs_ub; }});
308 407: sthx({{ Mem_uh = Rs_uh; }});
309 151: stwx({{ Mem = Rs; }});
310 150: stwcx({{
311 bool store_performed = false;
| 1// -*- mode:c++ -*-
2
3// Copyright (c) 2009 The University of Edinburgh
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Timothy M. Jones
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual Power ISA decoder
34// ------------------------------
35//
36// I've used the Power ISA Book I v2.06 for instruction formats,
37// opcode numbers, register names, etc.
38//
39decode OPCODE default Unknown::unknown() {
40
41 format IntImmOp {
42 10: cmpli({{
43 Xer xer = XER;
44 uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so);
45 CR = insertCRField(CR, BF, cr);
46 }});
47 11: cmpi({{
48 Xer xer = XER;
49 uint32_t cr = makeCRField(Ra_sw, (int32_t)imm, xer.so);
50 CR = insertCRField(CR, BF, cr);
51 }});
52 }
53
54 // Some instructions use bits 21 - 30, others 22 - 30. We have to use
55 // the larger size to account for all opcodes. For those that use the
56 // smaller value, the OE bit is bit 21. Therefore, we have two versions
57 // of each instruction: 1 with OE set, the other without. For an
58 // example see 'add' and 'addo'.
59 31: decode XO_XO {
60
61 // These instructions can all be reduced to the form
62 // Rt = src1 + src2 [+ CA], therefore we just give src1 and src2
63 // (and, if necessary, CA) definitions and let the python script
64 // deal with setting things up correctly. We also give flags to
65 // say which control registers to set.
66 format IntSumOp {
67 266: add({{ Ra }}, {{ Rb }});
68 40: subf({{ ~Ra }}, {{ Rb }}, {{ 1 }});
69 10: addc({{ Ra }}, {{ Rb }},
70 computeCA = true);
71 8: subfc({{ ~Ra }}, {{ Rb }}, {{ 1 }},
72 true);
73 104: neg({{ ~Ra }}, {{ 1 }});
74 138: adde({{ Ra }}, {{ Rb }}, {{ xer.ca }},
75 true);
76 234: addme({{ Ra }}, {{ (uint32_t)-1 }}, {{ xer.ca }},
77 true);
78 136: subfe({{ ~Ra }}, {{ Rb }}, {{ xer.ca }},
79 true);
80 232: subfme({{ ~Ra }}, {{ (uint32_t)-1 }}, {{ xer.ca }},
81 true);
82 202: addze({{ Ra }}, {{ xer.ca }},
83 computeCA = true);
84 200: subfze({{ ~Ra }}, {{ xer.ca }},
85 computeCA = true);
86 }
87
88 // Arithmetic instructions all use source registers Ra and Rb,
89 // with destination register Rt.
90 format IntArithOp {
91 75: mulhw({{ int64_t prod = Ra_sq * Rb_sq; Rt = prod >> 32; }});
92 11: mulhwu({{ uint64_t prod = Ra_uq * Rb_uq; Rt = prod >> 32; }});
93 235: mullw({{ int64_t prod = Ra_sq * Rb_sq; Rt = prod; }});
94 747: mullwo({{ int64_t src1 = Ra_sq; int64_t src2 = Rb; int64_t prod = src1 * src2; Rt = prod; }},
95 true);
96
97 491: divw({{
98 int32_t src1 = Ra_sw;
99 int32_t src2 = Rb_sw;
100 if ((src1 != 0x80000000 || src2 != 0xffffffff)
101 && src2 != 0) {
102 Rt = src1 / src2;
103 } else {
104 Rt = 0;
105 }
106 }});
107
108 1003: divwo({{
109 int32_t src1 = Ra_sw;
110 int32_t src2 = Rb_sw;
111 if ((src1 != 0x80000000 || src2 != 0xffffffff)
112 && src2 != 0) {
113 Rt = src1 / src2;
114 } else {
115 Rt = 0;
116 divSetOV = true;
117 }
118 }},
119 true);
120
121 459: divwu({{
122 uint32_t src1 = Ra_sw;
123 uint32_t src2 = Rb_sw;
124 if (src2 != 0) {
125 Rt = src1 / src2;
126 } else {
127 Rt = 0;
128 }
129 }});
130
131 971: divwuo({{
132 uint32_t src1 = Ra_sw;
133 uint32_t src2 = Rb_sw;
134 if (src2 != 0) {
135 Rt = src1 / src2;
136 } else {
137 Rt = 0;
138 divSetOV = true;
139 }
140 }},
141 true);
142 }
143
144 // Integer logic instructions use source registers Rs and Rb,
145 // with destination register Ra.
146 format IntLogicOp {
147 28: and({{ Ra = Rs & Rb; }});
148 316: xor({{ Ra = Rs ^ Rb; }});
149 476: nand({{ Ra = ~(Rs & Rb); }});
150 444: or({{ Ra = Rs | Rb; }});
151 124: nor({{ Ra = ~(Rs | Rb); }});
152 60: andc({{ Ra = Rs & ~Rb; }});
153 954: extsb({{ Ra = sext<8>(Rs); }});
154 284: eqv({{ Ra = ~(Rs ^ Rb); }});
155 412: orc({{ Ra = Rs | ~Rb; }});
156 922: extsh({{ Ra = sext<16>(Rs); }});
157 26: cntlzw({{ Ra = Rs == 0 ? 32 : 31 - findMsbSet(Rs); }});
158 508: cmpb({{
159 uint32_t val = 0;
160 for (int n = 0; n < 32; n += 8) {
161 if(bits(Rs, n, n+7) == bits(Rb, n, n+7)) {
162 val = insertBits(val, n, n+7, 0xff);
163 }
164 }
165 Ra = val;
166 }});
167
168 24: slw({{
169 if (Rb & 0x20) {
170 Ra = 0;
171 } else {
172 Ra = Rs << (Rb & 0x1f);
173 }
174 }});
175
176 536: srw({{
177 if (Rb & 0x20) {
178 Ra = 0;
179 } else {
180 Ra = Rs >> (Rb & 0x1f);
181 }
182 }});
183
184 792: sraw({{
185 bool shiftSetCA = false;
186 int32_t s = Rs;
187 if (Rb == 0) {
188 Ra = Rs;
189 shiftSetCA = true;
190 } else if (Rb & 0x20) {
191 if (s < 0) {
192 Ra = (uint32_t)-1;
193 if (s & 0x7fffffff) {
194 shiftSetCA = true;
195 } else {
196 shiftSetCA = false;
197 }
198 } else {
199 Ra = 0;
200 shiftSetCA = false;
201 }
202 } else {
203 Ra = s >> (Rb & 0x1f);
204 if (s < 0 && (s << (32 - (Rb & 0x1f))) != 0) {
205 shiftSetCA = true;
206 } else {
207 shiftSetCA = false;
208 }
209 }
210 Xer xer1 = XER;
211 if (shiftSetCA) {
212 xer1.ca = 1;
213 } else {
214 xer1.ca = 0;
215 }
216 XER = xer1;
217 }});
218 }
219
220 // Integer logic instructions with a shift value.
221 format IntShiftOp {
222 824: srawi({{
223 bool shiftSetCA = false;
224 if (sh == 0) {
225 Ra = Rs;
226 shiftSetCA = false;
227 } else {
228 int32_t s = Rs;
229 Ra = s >> sh;
230 if (s < 0 && (s << (32 - sh)) != 0) {
231 shiftSetCA = true;
232 } else {
233 shiftSetCA = false;
234 }
235 }
236 Xer xer1 = XER;
237 if (shiftSetCA) {
238 xer1.ca = 1;
239 } else {
240 xer1.ca = 0;
241 }
242 XER = xer1;
243 }});
244 }
245
246 // Generic integer format instructions.
247 format IntOp {
248 0: cmp({{
249 Xer xer = XER;
250 uint32_t cr = makeCRField(Ra_sw, Rb_sw, xer.so);
251 CR = insertCRField(CR, BF, cr);
252 }});
253 32: cmpl({{
254 Xer xer = XER;
255 uint32_t cr = makeCRField(Ra, Rb, xer.so);
256 CR = insertCRField(CR, BF, cr);
257 }});
258 144: mtcrf({{
259 uint32_t mask = 0;
260 for (int i = 0; i < 8; ++i) {
261 if (((FXM >> i) & 0x1) == 0x1) {
262 mask |= 0xf << (4 * i);
263 }
264 }
265 CR = (Rs & mask) | (CR & ~mask);
266 }});
267 19: mfcr({{ Rt = CR; }});
268 339: decode SPR {
269 0x20: mfxer({{ Rt = XER; }});
270 0x100: mflr({{ Rt = LR; }});
271 0x120: mfctr({{ Rt = CTR; }});
272 }
273 467: decode SPR {
274 0x20: mtxer({{ XER = Rs; }});
275 0x100: mtlr({{ LR = Rs; }});
276 0x120: mtctr({{ CTR = Rs; }});
277 }
278 }
279
280 // All loads with an index register. The non-update versions
281 // all use the value 0 if Ra == R0, not the value contained in
282 // R0. Others update Ra with the effective address. In all cases,
283 // Ra and Rb are source registers, Rt is the destintation.
284 format LoadIndexOp {
285 87: lbzx({{ Rt = Mem_ub; }});
286 279: lhzx({{ Rt = Mem_uh; }});
287 343: lhax({{ Rt = Mem_sh; }});
288 23: lwzx({{ Rt = Mem; }});
289 341: lwax({{ Rt = Mem_sw; }});
290 20: lwarx({{ Rt = Mem_sw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
291 535: lfsx({{ Ft_sf = Mem_sf; }});
292 599: lfdx({{ Ft = Mem_df; }});
293 855: lfiwax({{ Ft_uw = Mem; }});
294 }
295
296 format LoadIndexUpdateOp {
297 119: lbzux({{ Rt = Mem_ub; }});
298 311: lhzux({{ Rt = Mem_uh; }});
299 375: lhaux({{ Rt = Mem_sh; }});
300 55: lwzux({{ Rt = Mem; }});
301 373: lwaux({{ Rt = Mem_sw; }});
302 567: lfsux({{ Ft_sf = Mem_sf; }});
303 631: lfdux({{ Ft = Mem_df; }});
304 }
305
306 format StoreIndexOp {
307 215: stbx({{ Mem_ub = Rs_ub; }});
308 407: sthx({{ Mem_uh = Rs_uh; }});
309 151: stwx({{ Mem = Rs; }});
310 150: stwcx({{
311 bool store_performed = false;
|
316 store_performed = true;
317 }
318 }
319 }
320 Xer xer = XER;
321 Cr cr = CR;
322 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
323 CR = cr;
324 Rsv = 0;
325 }});
326 663: stfsx({{ Mem_sf = Fs_sf; }});
327 727: stfdx({{ Mem_df = Fs; }});
328 983: stfiwx({{ Mem = Fs_uw; }});
329 }
330
331 format StoreIndexUpdateOp {
332 247: stbux({{ Mem_ub = Rs_ub; }});
333 439: sthux({{ Mem_uh = Rs_uh; }});
334 183: stwux({{ Mem = Rs; }});
335 695: stfsux({{ Mem_sf = Fs_sf; }});
336 759: stfdux({{ Mem_df = Fs; }});
337 }
338
339 // These instructions all provide data cache hints
340 format MiscOp {
341 278: dcbt({{ }});
342 246: dcbtst({{ }});
343 598: sync({{ }}, [ IsMemBarrier ]);
344 854: eieio({{ }}, [ IsMemBarrier ]);
345 }
346 }
347
348 format IntImmArithCheckRaOp {
349 14: addi({{ Rt = Ra + imm; }},
350 {{ Rt = imm }});
351 15: addis({{ Rt = Ra + (imm << 16); }},
352 {{ Rt = imm << 16; }});
353 }
354
355 format IntImmArithOp {
356 12: addic({{ uint32_t src = Ra; Rt = src + imm; }},
357 [computeCA]);
358 13: addic_({{ uint32_t src = Ra; Rt = src + imm; }},
359 [computeCA, computeCR0]);
360 8: subfic({{ int32_t src = ~Ra; Rt = src + imm + 1; }},
361 [computeCA]);
362 7: mulli({{
363 int32_t src = Ra_sw;
364 int64_t prod = src * imm;
365 Rt = (uint32_t)prod;
366 }});
367 }
368
369 format IntImmLogicOp {
370 24: ori({{ Ra = Rs | uimm; }});
371 25: oris({{ Ra = Rs | (uimm << 16); }});
372 26: xori({{ Ra = Rs ^ uimm; }});
373 27: xoris({{ Ra = Rs ^ (uimm << 16); }});
374 28: andi_({{ Ra = Rs & uimm; }},
375 true);
376 29: andis_({{ Ra = Rs & (uimm << 16); }},
377 true);
378 }
379
380 16: decode AA {
381
382 // Conditionally branch relative to PC based on CR and CTR.
383 format BranchPCRelCondCtr {
384 0: bc({{ NPC = (uint32_t)(PC + disp); }});
385 }
386
387 // Conditionally branch to fixed address based on CR and CTR.
388 format BranchNonPCRelCondCtr {
389 1: bca({{ NPC = targetAddr; }});
390 }
391 }
392
393 18: decode AA {
394
395 // Unconditionally branch relative to PC.
396 format BranchPCRel {
397 0: b({{ NPC = (uint32_t)(PC + disp); }});
398 }
399
400 // Unconditionally branch to fixed address.
401 format BranchNonPCRel {
402 1: ba({{ NPC = targetAddr; }});
403 }
404 }
405
406 19: decode XO_XO {
407
408 // Conditionally branch to address in LR based on CR and CTR.
409 format BranchLrCondCtr {
410 16: bclr({{ NPC = LR & 0xfffffffc; }});
411 }
412
413 // Conditionally branch to address in CTR based on CR.
414 format BranchCtrCond {
415 528: bcctr({{ NPC = CTR & 0xfffffffc; }});
416 }
417
418 // Condition register manipulation instructions.
419 format CondLogicOp {
420 257: crand({{
421 uint32_t crBa = bits(CR, 31 - ba);
422 uint32_t crBb = bits(CR, 31 - bb);
423 CR = insertBits(CR, 31 - bt, crBa & crBb);
424 }});
425 449: cror({{
426 uint32_t crBa = bits(CR, 31 - ba);
427 uint32_t crBb = bits(CR, 31 - bb);
428 CR = insertBits(CR, 31 - bt, crBa | crBb);
429 }});
430 255: crnand({{
431 uint32_t crBa = bits(CR, 31 - ba);
432 uint32_t crBb = bits(CR, 31 - bb);
433 CR = insertBits(CR, 31 - bt, !(crBa & crBb));
434 }});
435 193: crxor({{
436 uint32_t crBa = bits(CR, 31 - ba);
437 uint32_t crBb = bits(CR, 31 - bb);
438 CR = insertBits(CR, 31 - bt, crBa ^ crBb);
439 }});
440 33: crnor({{
441 uint32_t crBa = bits(CR, 31 - ba);
442 uint32_t crBb = bits(CR, 31 - bb);
443 CR = insertBits(CR, 31 - bt, !(crBa | crBb));
444 }});
445 289: creqv({{
446 uint32_t crBa = bits(CR, 31 - ba);
447 uint32_t crBb = bits(CR, 31 - bb);
448 CR = insertBits(CR, 31 - bt, crBa == crBb);
449 }});
450 129: crandc({{
451 uint32_t crBa = bits(CR, 31 - ba);
452 uint32_t crBb = bits(CR, 31 - bb);
453 CR = insertBits(CR, 31 - bt, crBa & !crBb);
454 }});
455 417: crorc({{
456 uint32_t crBa = bits(CR, 31 - ba);
457 uint32_t crBb = bits(CR, 31 - bb);
458 CR = insertBits(CR, 31 - bt, crBa | !crBb);
459 }});
460 }
461 format CondMoveOp {
462 0: mcrf({{
463 uint32_t crBfa = bits(CR, 31 - bfa*4, 28 - bfa*4);
464 CR = insertBits(CR, 31 - bf*4, 28 - bf*4, crBfa);
465 }});
466 }
467 format MiscOp {
468 150: isync({{ }}, [ IsSerializeAfter ]);
469 }
470 }
471
472 format IntRotateOp {
473 21: rlwinm({{ Ra = rotateValue(Rs, sh) & fullMask; }});
474 23: rlwnm({{ Ra = rotateValue(Rs, Rb) & fullMask; }});
475 20: rlwimi({{ Ra = (rotateValue(Rs, sh) & fullMask) | (Ra & ~fullMask); }});
476 }
477
478 format LoadDispOp {
479 34: lbz({{ Rt = Mem_ub; }});
480 40: lhz({{ Rt = Mem_uh; }});
481 42: lha({{ Rt = Mem_sh; }});
482 32: lwz({{ Rt = Mem; }});
483 58: lwa({{ Rt = Mem_sw; }},
484 {{ EA = Ra + (disp & 0xfffffffc); }},
485 {{ EA = disp & 0xfffffffc; }});
486 48: lfs({{ Ft_sf = Mem_sf; }});
487 50: lfd({{ Ft = Mem_df; }});
488 }
489
490 format LoadDispUpdateOp {
491 35: lbzu({{ Rt = Mem_ub; }});
492 41: lhzu({{ Rt = Mem_uh; }});
493 43: lhau({{ Rt = Mem_sh; }});
494 33: lwzu({{ Rt = Mem; }});
495 49: lfsu({{ Ft_sf = Mem_sf; }});
496 51: lfdu({{ Ft = Mem_df; }});
497 }
498
499 format StoreDispOp {
500 38: stb({{ Mem_ub = Rs_ub; }});
501 44: sth({{ Mem_uh = Rs_uh; }});
502 36: stw({{ Mem = Rs; }});
503 52: stfs({{ Mem_sf = Fs_sf; }});
504 54: stfd({{ Mem_df = Fs; }});
505 }
506
507 format StoreDispUpdateOp {
508 39: stbu({{ Mem_ub = Rs_ub; }});
509 45: sthu({{ Mem_uh = Rs_uh; }});
510 37: stwu({{ Mem = Rs; }});
511 53: stfsu({{ Mem_sf = Fs_sf; }});
512 55: stfdu({{ Mem_df = Fs; }});
513 }
514
515 17: IntOp::sc({{ xc->syscall(R0); }},
516 [ IsSyscall, IsNonSpeculative, IsSerializeAfter ]);
517
518 format FloatArithOp {
519 59: decode A_XO {
520 21: fadds({{ Ft = Fa + Fb; }});
521 20: fsubs({{ Ft = Fa - Fb; }});
522 25: fmuls({{ Ft = Fa * Fc; }});
523 18: fdivs({{ Ft = Fa / Fb; }});
524 29: fmadds({{ Ft = (Fa * Fc) + Fb; }});
525 28: fmsubs({{ Ft = (Fa * Fc) - Fb; }});
526 31: fnmadds({{ Ft = -((Fa * Fc) + Fb); }});
527 30: fnmsubs({{ Ft = -((Fa * Fc) - Fb); }});
528 }
529 }
530
531 63: decode A_XO {
532 format FloatArithOp {
533 21: fadd({{ Ft = Fa + Fb; }});
534 20: fsub({{ Ft = Fa - Fb; }});
535 25: fmul({{ Ft = Fa * Fc; }});
536 18: fdiv({{ Ft = Fa / Fb; }});
537 29: fmadd({{ Ft = (Fa * Fc) + Fb; }});
538 28: fmsub({{ Ft = (Fa * Fc) - Fb; }});
539 31: fnmadd({{ Ft = -((Fa * Fc) + Fb); }});
540 30: fnmsub({{ Ft = -((Fa * Fc) - Fb); }});
541 }
542
543 default: decode XO_XO {
544 format FloatConvertOp {
545 12: frsp({{ Ft_sf = Fb; }});
546 15: fctiwz({{ Ft_sw = (int32_t)trunc(Fb); }});
547 }
548
549 format FloatOp {
550 0: fcmpu({{
551 uint32_t c = makeCRField(Fa, Fb);
552 Fpscr fpscr = FPSCR;
553 fpscr.fprf.fpcc = c;
554 FPSCR = fpscr;
555 CR = insertCRField(CR, BF, c);
556 }});
557 }
558
559 format FloatRCCheckOp {
560 72: fmr({{ Ft = Fb; }});
561 264: fabs({{
562 Ft_uq = Fb_uq;
563 Ft_uq = insertBits(Ft_uq, 63, 0); }});
564 136: fnabs({{
565 Ft_uq = Fb_uq;
566 Ft_uq = insertBits(Ft_uq, 63, 1); }});
567 40: fneg({{ Ft = -Fb; }});
568 8: fcpsgn({{
569 Ft_uq = Fb_uq;
570 Ft_uq = insertBits(Ft_uq, 63, Fa_uq<63:63>);
571 }});
572 583: mffs({{ Ft_uq = FPSCR; }});
573 134: mtfsfi({{
574 FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W_FIELD)),
575 U_FIELD);
576 }});
577 711: mtfsf({{
578 if (L_FIELD == 1) { FPSCR = Fb_uq; }
579 else {
580 for (int i = 0; i < 8; ++i) {
581 if (bits(FLM, i) == 1) {
582 int k = 4 * (i + (8 * (1 - W_FIELD)));
583 FPSCR = insertBits(FPSCR, k, k + 3,
584 bits(Fb_uq, k, k + 3));
585 }
586 }
587 }
588 }});
589 70: mtfsb0({{ FPSCR = insertBits(FPSCR, 31 - BT, 0); }});
590 38: mtfsb1({{ FPSCR = insertBits(FPSCR, 31 - BT, 1); }});
591 }
592 }
593 }
594}
| 316 store_performed = true;
317 }
318 }
319 }
320 Xer xer = XER;
321 Cr cr = CR;
322 cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so);
323 CR = cr;
324 Rsv = 0;
325 }});
326 663: stfsx({{ Mem_sf = Fs_sf; }});
327 727: stfdx({{ Mem_df = Fs; }});
328 983: stfiwx({{ Mem = Fs_uw; }});
329 }
330
331 format StoreIndexUpdateOp {
332 247: stbux({{ Mem_ub = Rs_ub; }});
333 439: sthux({{ Mem_uh = Rs_uh; }});
334 183: stwux({{ Mem = Rs; }});
335 695: stfsux({{ Mem_sf = Fs_sf; }});
336 759: stfdux({{ Mem_df = Fs; }});
337 }
338
339 // These instructions all provide data cache hints
340 format MiscOp {
341 278: dcbt({{ }});
342 246: dcbtst({{ }});
343 598: sync({{ }}, [ IsMemBarrier ]);
344 854: eieio({{ }}, [ IsMemBarrier ]);
345 }
346 }
347
348 format IntImmArithCheckRaOp {
349 14: addi({{ Rt = Ra + imm; }},
350 {{ Rt = imm }});
351 15: addis({{ Rt = Ra + (imm << 16); }},
352 {{ Rt = imm << 16; }});
353 }
354
355 format IntImmArithOp {
356 12: addic({{ uint32_t src = Ra; Rt = src + imm; }},
357 [computeCA]);
358 13: addic_({{ uint32_t src = Ra; Rt = src + imm; }},
359 [computeCA, computeCR0]);
360 8: subfic({{ int32_t src = ~Ra; Rt = src + imm + 1; }},
361 [computeCA]);
362 7: mulli({{
363 int32_t src = Ra_sw;
364 int64_t prod = src * imm;
365 Rt = (uint32_t)prod;
366 }});
367 }
368
369 format IntImmLogicOp {
370 24: ori({{ Ra = Rs | uimm; }});
371 25: oris({{ Ra = Rs | (uimm << 16); }});
372 26: xori({{ Ra = Rs ^ uimm; }});
373 27: xoris({{ Ra = Rs ^ (uimm << 16); }});
374 28: andi_({{ Ra = Rs & uimm; }},
375 true);
376 29: andis_({{ Ra = Rs & (uimm << 16); }},
377 true);
378 }
379
380 16: decode AA {
381
382 // Conditionally branch relative to PC based on CR and CTR.
383 format BranchPCRelCondCtr {
384 0: bc({{ NPC = (uint32_t)(PC + disp); }});
385 }
386
387 // Conditionally branch to fixed address based on CR and CTR.
388 format BranchNonPCRelCondCtr {
389 1: bca({{ NPC = targetAddr; }});
390 }
391 }
392
393 18: decode AA {
394
395 // Unconditionally branch relative to PC.
396 format BranchPCRel {
397 0: b({{ NPC = (uint32_t)(PC + disp); }});
398 }
399
400 // Unconditionally branch to fixed address.
401 format BranchNonPCRel {
402 1: ba({{ NPC = targetAddr; }});
403 }
404 }
405
406 19: decode XO_XO {
407
408 // Conditionally branch to address in LR based on CR and CTR.
409 format BranchLrCondCtr {
410 16: bclr({{ NPC = LR & 0xfffffffc; }});
411 }
412
413 // Conditionally branch to address in CTR based on CR.
414 format BranchCtrCond {
415 528: bcctr({{ NPC = CTR & 0xfffffffc; }});
416 }
417
418 // Condition register manipulation instructions.
419 format CondLogicOp {
420 257: crand({{
421 uint32_t crBa = bits(CR, 31 - ba);
422 uint32_t crBb = bits(CR, 31 - bb);
423 CR = insertBits(CR, 31 - bt, crBa & crBb);
424 }});
425 449: cror({{
426 uint32_t crBa = bits(CR, 31 - ba);
427 uint32_t crBb = bits(CR, 31 - bb);
428 CR = insertBits(CR, 31 - bt, crBa | crBb);
429 }});
430 255: crnand({{
431 uint32_t crBa = bits(CR, 31 - ba);
432 uint32_t crBb = bits(CR, 31 - bb);
433 CR = insertBits(CR, 31 - bt, !(crBa & crBb));
434 }});
435 193: crxor({{
436 uint32_t crBa = bits(CR, 31 - ba);
437 uint32_t crBb = bits(CR, 31 - bb);
438 CR = insertBits(CR, 31 - bt, crBa ^ crBb);
439 }});
440 33: crnor({{
441 uint32_t crBa = bits(CR, 31 - ba);
442 uint32_t crBb = bits(CR, 31 - bb);
443 CR = insertBits(CR, 31 - bt, !(crBa | crBb));
444 }});
445 289: creqv({{
446 uint32_t crBa = bits(CR, 31 - ba);
447 uint32_t crBb = bits(CR, 31 - bb);
448 CR = insertBits(CR, 31 - bt, crBa == crBb);
449 }});
450 129: crandc({{
451 uint32_t crBa = bits(CR, 31 - ba);
452 uint32_t crBb = bits(CR, 31 - bb);
453 CR = insertBits(CR, 31 - bt, crBa & !crBb);
454 }});
455 417: crorc({{
456 uint32_t crBa = bits(CR, 31 - ba);
457 uint32_t crBb = bits(CR, 31 - bb);
458 CR = insertBits(CR, 31 - bt, crBa | !crBb);
459 }});
460 }
461 format CondMoveOp {
462 0: mcrf({{
463 uint32_t crBfa = bits(CR, 31 - bfa*4, 28 - bfa*4);
464 CR = insertBits(CR, 31 - bf*4, 28 - bf*4, crBfa);
465 }});
466 }
467 format MiscOp {
468 150: isync({{ }}, [ IsSerializeAfter ]);
469 }
470 }
471
472 format IntRotateOp {
473 21: rlwinm({{ Ra = rotateValue(Rs, sh) & fullMask; }});
474 23: rlwnm({{ Ra = rotateValue(Rs, Rb) & fullMask; }});
475 20: rlwimi({{ Ra = (rotateValue(Rs, sh) & fullMask) | (Ra & ~fullMask); }});
476 }
477
478 format LoadDispOp {
479 34: lbz({{ Rt = Mem_ub; }});
480 40: lhz({{ Rt = Mem_uh; }});
481 42: lha({{ Rt = Mem_sh; }});
482 32: lwz({{ Rt = Mem; }});
483 58: lwa({{ Rt = Mem_sw; }},
484 {{ EA = Ra + (disp & 0xfffffffc); }},
485 {{ EA = disp & 0xfffffffc; }});
486 48: lfs({{ Ft_sf = Mem_sf; }});
487 50: lfd({{ Ft = Mem_df; }});
488 }
489
490 format LoadDispUpdateOp {
491 35: lbzu({{ Rt = Mem_ub; }});
492 41: lhzu({{ Rt = Mem_uh; }});
493 43: lhau({{ Rt = Mem_sh; }});
494 33: lwzu({{ Rt = Mem; }});
495 49: lfsu({{ Ft_sf = Mem_sf; }});
496 51: lfdu({{ Ft = Mem_df; }});
497 }
498
499 format StoreDispOp {
500 38: stb({{ Mem_ub = Rs_ub; }});
501 44: sth({{ Mem_uh = Rs_uh; }});
502 36: stw({{ Mem = Rs; }});
503 52: stfs({{ Mem_sf = Fs_sf; }});
504 54: stfd({{ Mem_df = Fs; }});
505 }
506
507 format StoreDispUpdateOp {
508 39: stbu({{ Mem_ub = Rs_ub; }});
509 45: sthu({{ Mem_uh = Rs_uh; }});
510 37: stwu({{ Mem = Rs; }});
511 53: stfsu({{ Mem_sf = Fs_sf; }});
512 55: stfdu({{ Mem_df = Fs; }});
513 }
514
515 17: IntOp::sc({{ xc->syscall(R0); }},
516 [ IsSyscall, IsNonSpeculative, IsSerializeAfter ]);
517
518 format FloatArithOp {
519 59: decode A_XO {
520 21: fadds({{ Ft = Fa + Fb; }});
521 20: fsubs({{ Ft = Fa - Fb; }});
522 25: fmuls({{ Ft = Fa * Fc; }});
523 18: fdivs({{ Ft = Fa / Fb; }});
524 29: fmadds({{ Ft = (Fa * Fc) + Fb; }});
525 28: fmsubs({{ Ft = (Fa * Fc) - Fb; }});
526 31: fnmadds({{ Ft = -((Fa * Fc) + Fb); }});
527 30: fnmsubs({{ Ft = -((Fa * Fc) - Fb); }});
528 }
529 }
530
531 63: decode A_XO {
532 format FloatArithOp {
533 21: fadd({{ Ft = Fa + Fb; }});
534 20: fsub({{ Ft = Fa - Fb; }});
535 25: fmul({{ Ft = Fa * Fc; }});
536 18: fdiv({{ Ft = Fa / Fb; }});
537 29: fmadd({{ Ft = (Fa * Fc) + Fb; }});
538 28: fmsub({{ Ft = (Fa * Fc) - Fb; }});
539 31: fnmadd({{ Ft = -((Fa * Fc) + Fb); }});
540 30: fnmsub({{ Ft = -((Fa * Fc) - Fb); }});
541 }
542
543 default: decode XO_XO {
544 format FloatConvertOp {
545 12: frsp({{ Ft_sf = Fb; }});
546 15: fctiwz({{ Ft_sw = (int32_t)trunc(Fb); }});
547 }
548
549 format FloatOp {
550 0: fcmpu({{
551 uint32_t c = makeCRField(Fa, Fb);
552 Fpscr fpscr = FPSCR;
553 fpscr.fprf.fpcc = c;
554 FPSCR = fpscr;
555 CR = insertCRField(CR, BF, c);
556 }});
557 }
558
559 format FloatRCCheckOp {
560 72: fmr({{ Ft = Fb; }});
561 264: fabs({{
562 Ft_uq = Fb_uq;
563 Ft_uq = insertBits(Ft_uq, 63, 0); }});
564 136: fnabs({{
565 Ft_uq = Fb_uq;
566 Ft_uq = insertBits(Ft_uq, 63, 1); }});
567 40: fneg({{ Ft = -Fb; }});
568 8: fcpsgn({{
569 Ft_uq = Fb_uq;
570 Ft_uq = insertBits(Ft_uq, 63, Fa_uq<63:63>);
571 }});
572 583: mffs({{ Ft_uq = FPSCR; }});
573 134: mtfsfi({{
574 FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W_FIELD)),
575 U_FIELD);
576 }});
577 711: mtfsf({{
578 if (L_FIELD == 1) { FPSCR = Fb_uq; }
579 else {
580 for (int i = 0; i < 8; ++i) {
581 if (bits(FLM, i) == 1) {
582 int k = 4 * (i + (8 * (1 - W_FIELD)));
583 FPSCR = insertBits(FPSCR, k, k + 3,
584 bits(Fb_uq, k, k + 3));
585 }
586 }
587 }
588 }});
589 70: mtfsb0({{ FPSCR = insertBits(FPSCR, 31 - BT, 0); }});
590 38: mtfsb1({{ FPSCR = insertBits(FPSCR, 31 - BT, 1); }});
591 }
592 }
593 }
594}
|