isa.hh (12334:e0ab29a34764) isa.hh (13582:989577bf6abc)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * Copyright (c) 2009 The University of Edinburgh
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 62 unchanged lines hidden (view full) ---

71 MiscReg
72 readMiscReg(int misc_reg, ThreadContext *tc)
73 {
74 fatal("Power does not currently have any misc regs defined\n");
75 return dummy;
76 }
77
78 void
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * Copyright (c) 2009 The University of Edinburgh
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

--- 62 unchanged lines hidden (view full) ---

71 MiscReg
72 readMiscReg(int misc_reg, ThreadContext *tc)
73 {
74 fatal("Power does not currently have any misc regs defined\n");
75 return dummy;
76 }
77
78 void
79 setMiscRegNoEffect(int misc_reg, const MiscReg &val)
79 setMiscRegNoEffect(int misc_reg, MiscReg val)
80 {
81 fatal("Power does not currently have any misc regs defined\n");
82 }
83
84 void
80 {
81 fatal("Power does not currently have any misc regs defined\n");
82 }
83
84 void
85 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
85 setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc)
86 {
87 fatal("Power does not currently have any misc regs defined\n");
88 }
89
90 RegId flattenRegId(const RegId& regId) const { return regId; }
91
92 int
93 flattenIntIndex(int reg) const

--- 48 unchanged lines hidden --- 		86 {
87 fatal("Power does not currently have any misc regs defined\n");
88 }
89
90 RegId flattenRegId(const RegId& regId) const { return regId; }
91
92 int
93 flattenIntIndex(int reg) const

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