isa.hh (10935:acd48ddd725f) | isa.hh (12106:7784fac1b159) |
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1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * Copyright (c) 2009 The University of Edinburgh 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 22 unchanged lines hidden (view full) --- 31 */ 32 33#ifndef __ARCH_POWER_ISA_HH__ 34#define __ARCH_POWER_ISA_HH__ 35 36#include "arch/power/registers.hh" 37#include "arch/power/types.hh" 38#include "base/misc.hh" | 1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * Copyright (c) 2009 The University of Edinburgh 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 22 unchanged lines hidden (view full) --- 31 */ 32 33#ifndef __ARCH_POWER_ISA_HH__ 34#define __ARCH_POWER_ISA_HH__ 35 36#include "arch/power/registers.hh" 37#include "arch/power/types.hh" 38#include "base/misc.hh" |
39#include "cpu/reg_class.hh" |
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39#include "sim/sim_object.hh" 40 41struct PowerISAParams; 42class ThreadContext; 43class Checkpoint; 44class EventManager; 45 46namespace PowerISA --- 34 unchanged lines hidden (view full) --- 81 } 82 83 void 84 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 85 { 86 fatal("Power does not currently have any misc regs defined\n"); 87 } 88 | 40#include "sim/sim_object.hh" 41 42struct PowerISAParams; 43class ThreadContext; 44class Checkpoint; 45class EventManager; 46 47namespace PowerISA --- 34 unchanged lines hidden (view full) --- 82 } 83 84 void 85 setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 86 { 87 fatal("Power does not currently have any misc regs defined\n"); 88 } 89 |
90 RegId flattenRegId(const RegId& regId) const { return regId; } 91 |
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89 int 90 flattenIntIndex(int reg) const 91 { 92 return reg; 93 } 94 95 int 96 flattenFloatIndex(int reg) const --- 30 unchanged lines hidden --- | 92 int 93 flattenIntIndex(int reg) const 94 { 95 return reg; 96 } 97 98 int 99 flattenFloatIndex(int reg) const --- 30 unchanged lines hidden --- |