1/* Copyright (c) 2007-2008 The Florida State University 2 * Copyright (c) 2009 The University of Edinburgh 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 72 unchanged lines hidden (view full) --- 81 disp(machInst.li << 2) 82 { 83 // If bit 26 is 1 then sign extend 84 if (disp & 0x2000000) { 85 disp |= 0xfc000000; 86 } 87 } 88 |
89 PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override; |
90 91 /// Explicitly import the otherwise hidden branchTarget 92 using StaticInst::branchTarget; 93 |
94 std::string generateDisassembly( 95 Addr pc, const SymbolTable *symtab) const override; |
96}; 97 98/** 99 * Base class for unconditional, non PC-relative branches. 100 */ 101class BranchNonPCRel : public PCDependentDisassembly 102{ 103 protected: --- 7 unchanged lines hidden (view full) --- 111 targetAddr(machInst.li << 2) 112 { 113 // If bit 26 is 1 then sign extend 114 if (targetAddr & 0x2000000) { 115 targetAddr |= 0xfc000000; 116 } 117 } 118 |
119 PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override; |
120 121 /// Explicitly import the otherwise hidden branchTarget 122 using StaticInst::branchTarget; 123 |
124 std::string generateDisassembly( 125 Addr pc, const SymbolTable *symtab) const override; |
126}; 127 128/** 129 * Base class for conditional branches. 130 */ 131class BranchCond : public PCDependentDisassembly 132{ 133 protected: --- 56 unchanged lines hidden (view full) --- 190 disp(machInst.bd << 2) 191 { 192 // If bit 16 is 1 then sign extend 193 if (disp & 0x8000) { 194 disp |= 0xffff0000; 195 } 196 } 197 |
198 PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override; |
199 200 /// Explicitly import the otherwise hidden branchTarget 201 using StaticInst::branchTarget; 202 |
203 std::string generateDisassembly( 204 Addr pc, const SymbolTable *symtab) const override; |
205}; 206 207/** 208 * Base class for conditional, non PC-relative branches. 209 */ 210class BranchNonPCRelCond : public BranchCond 211{ 212 protected: --- 7 unchanged lines hidden (view full) --- 220 targetAddr(machInst.bd << 2) 221 { 222 // If bit 16 is 1 then sign extend 223 if (targetAddr & 0x8000) { 224 targetAddr |= 0xffff0000; 225 } 226 } 227 |
228 PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const override; |
229 230 /// Explicitly import the otherwise hidden branchTarget 231 using StaticInst::branchTarget; 232 |
233 std::string generateDisassembly( 234 Addr pc, const SymbolTable *symtab) const override; |
235}; 236 237/** 238 * Base class for conditional, register-based branches 239 */ 240class BranchRegCond : public BranchCond 241{ 242 protected: 243 244 /// Constructor. 245 BranchRegCond(const char *mnem, MachInst _machInst, OpClass __opClass) 246 : BranchCond(mnem, _machInst, __opClass) 247 { 248 } 249 |
250 PowerISA::PCState branchTarget(ThreadContext *tc) const override; |
251 252 /// Explicitly import the otherwise hidden branchTarget 253 using StaticInst::branchTarget; 254 |
255 std::string generateDisassembly( 256 Addr pc, const SymbolTable *symtab) const override; |
257}; 258 259} // namespace PowerISA 260 261#endif //__ARCH_POWER_INSTS_BRANCH_HH__ |