1/* Copyright (c) 2007-2008 The Florida State University
2 * Copyright (c) 2009 The University of Edinburgh
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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81 disp(machInst.li << 2)
82 {
83 // If bit 26 is 1 then sign extend
84 if (disp & 0x2000000) {
85 disp |= 0xfc000000;
86 }
87 }
88
89 PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const;
90
91 /// Explicitly import the otherwise hidden branchTarget
92 using StaticInst::branchTarget;
93
94 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
95};
96
97/**
98 * Base class for unconditional, non PC-relative branches.
99 */
100class BranchNonPCRel : public PCDependentDisassembly
101{
102 protected:

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110 targetAddr(machInst.li << 2)
111 {
112 // If bit 26 is 1 then sign extend
113 if (targetAddr & 0x2000000) {
114 targetAddr |= 0xfc000000;
115 }
116 }
117
118 PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const;
119
120 /// Explicitly import the otherwise hidden branchTarget
121 using StaticInst::branchTarget;
122
123 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
124};
125
126/**
127 * Base class for conditional branches.
128 */
129class BranchCond : public PCDependentDisassembly
130{
131 protected:

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188 disp(machInst.bd << 2)
189 {
190 // If bit 16 is 1 then sign extend
191 if (disp & 0x8000) {
192 disp |= 0xffff0000;
193 }
194 }
195
196 PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const;
197
198 /// Explicitly import the otherwise hidden branchTarget
199 using StaticInst::branchTarget;
200
201 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
202};
203
204/**
205 * Base class for conditional, non PC-relative branches.
206 */
207class BranchNonPCRelCond : public BranchCond
208{
209 protected:

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217 targetAddr(machInst.bd << 2)
218 {
219 // If bit 16 is 1 then sign extend
220 if (targetAddr & 0x8000) {
221 targetAddr |= 0xffff0000;
222 }
223 }
224
225 PowerISA::PCState branchTarget(const PowerISA::PCState &pc) const;
226
227 /// Explicitly import the otherwise hidden branchTarget
228 using StaticInst::branchTarget;
229
230 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
231};
232
233/**
234 * Base class for conditional, register-based branches
235 */
236class BranchRegCond : public BranchCond
237{
238 protected:
239
240 /// Constructor.
241 BranchRegCond(const char *mnem, MachInst _machInst, OpClass __opClass)
242 : BranchCond(mnem, _machInst, __opClass)
243 {
244 }
245
246 PowerISA::PCState branchTarget(ThreadContext *tc) const;
247
248 /// Explicitly import the otherwise hidden branchTarget
249 using StaticInst::branchTarget;
250
251 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
252};
253
254} // namespace PowerISA
255
256#endif //__ARCH_POWER_INSTS_BRANCH_HH__