branch.cc (11793:ef606668d247) | branch.cc (12104:edd63f9c6184) |
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1/* 2 * Copyright (c) 2009 The University of Edinburgh 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 139 unchanged lines hidden (view full) --- 148 ccprintf(ss, "0x%x", targetAddr); 149 150 return ss.str(); 151} 152 153PowerISA::PCState 154BranchRegCond::branchTarget(ThreadContext *tc) const 155{ | 1/* 2 * Copyright (c) 2009 The University of Edinburgh 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 139 unchanged lines hidden (view full) --- 148 ccprintf(ss, "0x%x", targetAddr); 149 150 return ss.str(); 151} 152 153PowerISA::PCState 154BranchRegCond::branchTarget(ThreadContext *tc) const 155{ |
156 uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1]); | 156 uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1].regIdx); |
157 return regVal & 0xfffffffc; 158} 159 160std::string 161BranchRegCond::generateDisassembly(Addr pc, 162 const SymbolTable *symtab) const 163{ 164 std::stringstream ss; 165 166 ccprintf(ss, "%-10s ", mnemonic); 167 168 ss << bo << ", " << bi << ", "; 169 170 return ss.str(); 171} | 157 return regVal & 0xfffffffc; 158} 159 160std::string 161BranchRegCond::generateDisassembly(Addr pc, 162 const SymbolTable *symtab) const 163{ 164 std::stringstream ss; 165 166 ccprintf(ss, "%-10s ", mnemonic); 167 168 ss << bo << ", " << bi << ", "; 169 170 return ss.str(); 171} |