1/* 2 * Copyright (c) 2009 The University of Edinburgh 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Timothy M. Jones 29 */ 30 31#include "arch/power/insts/branch.hh"
| 1/* 2 * Copyright (c) 2009 The University of Edinburgh 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Timothy M. Jones 29 */ 30 31#include "arch/power/insts/branch.hh"
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32#include "base/loader/symtab.hh" 33#include "cpu/thread_context.hh" 34 35using namespace PowerISA; 36 37const std::string & 38PCDependentDisassembly::disassemble(Addr pc, const SymbolTable *symtab) const 39{ 40 if (!cachedDisassembly || 41 pc != cachedPC || symtab != cachedSymtab) 42 { 43 if (cachedDisassembly) 44 delete cachedDisassembly; 45 46 cachedDisassembly = 47 new std::string(generateDisassembly(pc, symtab)); 48 cachedPC = pc; 49 cachedSymtab = symtab; 50 } 51 52 return *cachedDisassembly; 53} 54 55PowerISA::PCState 56BranchPCRel::branchTarget(const PowerISA::PCState &pc) const 57{ 58 return (uint32_t)(pc.pc() + disp); 59} 60 61std::string 62BranchPCRel::generateDisassembly(Addr pc, const SymbolTable *symtab) const 63{ 64 std::stringstream ss; 65 66 ccprintf(ss, "%-10s ", mnemonic); 67 68 Addr target = pc + disp; 69 70 std::string str; 71 if (symtab && symtab->findSymbol(target, str)) 72 ss << str; 73 else 74 ccprintf(ss, "0x%x", target); 75 76 return ss.str(); 77} 78 79PowerISA::PCState 80BranchNonPCRel::branchTarget(const PowerISA::PCState &pc) const 81{ 82 return targetAddr; 83} 84 85std::string 86BranchNonPCRel::generateDisassembly(Addr pc, const SymbolTable *symtab) const 87{ 88 std::stringstream ss; 89 90 ccprintf(ss, "%-10s ", mnemonic); 91 92 std::string str; 93 if (symtab && symtab->findSymbol(targetAddr, str)) 94 ss << str; 95 else 96 ccprintf(ss, "0x%x", targetAddr); 97 98 return ss.str(); 99} 100 101PowerISA::PCState 102BranchPCRelCond::branchTarget(const PowerISA::PCState &pc) const 103{ 104 return (uint32_t)(pc.pc() + disp); 105} 106 107std::string 108BranchPCRelCond::generateDisassembly(Addr pc, const SymbolTable *symtab) const 109{ 110 std::stringstream ss; 111 112 ccprintf(ss, "%-10s ", mnemonic); 113 114 ss << bo << ", " << bi << ", "; 115 116 Addr target = pc + disp; 117 118 std::string str; 119 if (symtab && symtab->findSymbol(target, str)) 120 ss << str; 121 else 122 ccprintf(ss, "0x%x", target); 123 124 return ss.str(); 125} 126 127PowerISA::PCState 128BranchNonPCRelCond::branchTarget(const PowerISA::PCState &pc) const 129{ 130 return targetAddr; 131} 132 133std::string 134BranchNonPCRelCond::generateDisassembly(Addr pc, 135 const SymbolTable *symtab) const 136{ 137 std::stringstream ss; 138 139 ccprintf(ss, "%-10s ", mnemonic); 140 141 ss << bo << ", " << bi << ", "; 142 143 std::string str; 144 if (symtab && symtab->findSymbol(targetAddr, str)) 145 ss << str; 146 else 147 ccprintf(ss, "0x%x", targetAddr); 148 149 return ss.str(); 150} 151 152PowerISA::PCState 153BranchRegCond::branchTarget(ThreadContext *tc) const 154{ 155 uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1]); 156 return regVal & 0xfffffffc; 157} 158 159std::string 160BranchRegCond::generateDisassembly(Addr pc, 161 const SymbolTable *symtab) const 162{ 163 std::stringstream ss; 164 165 ccprintf(ss, "%-10s ", mnemonic); 166 167 ss << bo << ", " << bi << ", "; 168 169 return ss.str(); 170}
| 33#include "base/loader/symtab.hh" 34#include "cpu/thread_context.hh" 35 36using namespace PowerISA; 37 38const std::string & 39PCDependentDisassembly::disassemble(Addr pc, const SymbolTable *symtab) const 40{ 41 if (!cachedDisassembly || 42 pc != cachedPC || symtab != cachedSymtab) 43 { 44 if (cachedDisassembly) 45 delete cachedDisassembly; 46 47 cachedDisassembly = 48 new std::string(generateDisassembly(pc, symtab)); 49 cachedPC = pc; 50 cachedSymtab = symtab; 51 } 52 53 return *cachedDisassembly; 54} 55 56PowerISA::PCState 57BranchPCRel::branchTarget(const PowerISA::PCState &pc) const 58{ 59 return (uint32_t)(pc.pc() + disp); 60} 61 62std::string 63BranchPCRel::generateDisassembly(Addr pc, const SymbolTable *symtab) const 64{ 65 std::stringstream ss; 66 67 ccprintf(ss, "%-10s ", mnemonic); 68 69 Addr target = pc + disp; 70 71 std::string str; 72 if (symtab && symtab->findSymbol(target, str)) 73 ss << str; 74 else 75 ccprintf(ss, "0x%x", target); 76 77 return ss.str(); 78} 79 80PowerISA::PCState 81BranchNonPCRel::branchTarget(const PowerISA::PCState &pc) const 82{ 83 return targetAddr; 84} 85 86std::string 87BranchNonPCRel::generateDisassembly(Addr pc, const SymbolTable *symtab) const 88{ 89 std::stringstream ss; 90 91 ccprintf(ss, "%-10s ", mnemonic); 92 93 std::string str; 94 if (symtab && symtab->findSymbol(targetAddr, str)) 95 ss << str; 96 else 97 ccprintf(ss, "0x%x", targetAddr); 98 99 return ss.str(); 100} 101 102PowerISA::PCState 103BranchPCRelCond::branchTarget(const PowerISA::PCState &pc) const 104{ 105 return (uint32_t)(pc.pc() + disp); 106} 107 108std::string 109BranchPCRelCond::generateDisassembly(Addr pc, const SymbolTable *symtab) const 110{ 111 std::stringstream ss; 112 113 ccprintf(ss, "%-10s ", mnemonic); 114 115 ss << bo << ", " << bi << ", "; 116 117 Addr target = pc + disp; 118 119 std::string str; 120 if (symtab && symtab->findSymbol(target, str)) 121 ss << str; 122 else 123 ccprintf(ss, "0x%x", target); 124 125 return ss.str(); 126} 127 128PowerISA::PCState 129BranchNonPCRelCond::branchTarget(const PowerISA::PCState &pc) const 130{ 131 return targetAddr; 132} 133 134std::string 135BranchNonPCRelCond::generateDisassembly(Addr pc, 136 const SymbolTable *symtab) const 137{ 138 std::stringstream ss; 139 140 ccprintf(ss, "%-10s ", mnemonic); 141 142 ss << bo << ", " << bi << ", "; 143 144 std::string str; 145 if (symtab && symtab->findSymbol(targetAddr, str)) 146 ss << str; 147 else 148 ccprintf(ss, "0x%x", targetAddr); 149 150 return ss.str(); 151} 152 153PowerISA::PCState 154BranchRegCond::branchTarget(ThreadContext *tc) const 155{ 156 uint32_t regVal = tc->readIntReg(_srcRegIdx[_numSrcRegs - 1]); 157 return regVal & 0xfffffffc; 158} 159 160std::string 161BranchRegCond::generateDisassembly(Addr pc, 162 const SymbolTable *symtab) const 163{ 164 std::stringstream ss; 165 166 ccprintf(ss, "%-10s ", mnemonic); 167 168 ss << bo << ", " << bi << ", "; 169 170 return ss.str(); 171}
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