1/* 2 * Copyright (c) 2012 Google 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#ifndef __ARCH_POWER_DECODER_HH__ 32#define __ARCH_POWER_DECODER_HH__ 33
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34#include "arch/generic/decode_cache.hh" |
35#include "arch/types.hh"
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35#include "cpu/decode_cache.hh"
36#include "cpu/static_inst_fwd.hh"
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36#include "cpu/static_inst.hh" |
37
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38class ThreadContext; 39 |
40namespace PowerISA 41{ 42 43class Decoder 44{ 45 protected: 46 ThreadContext * tc; 47 48 // The extended machine instruction being generated 49 ExtMachInst emi; 50 bool instDone; 51 52 public: 53 Decoder(ThreadContext * _tc) : tc(_tc), instDone(false) 54 { 55 } 56 57 ThreadContext * 58 getTC() 59 { 60 return tc; 61 } 62 63 void 64 setTC(ThreadContext * _tc) 65 { 66 tc = _tc; 67 } 68 69 void 70 process() 71 { 72 } 73 74 void 75 reset() 76 { 77 instDone = false; 78 } 79 80 // Use this to give data to the predecoder. This should be used 81 // when there is control flow. 82 void 83 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) 84 { 85 emi = inst; 86 instDone = true; 87 } 88 89 // Use this to give data to the predecoder. This should be used 90 // when instructions are executed in order. 91 void 92 moreBytes(MachInst machInst) 93 { 94 moreBytes(0, 0, machInst); 95 } 96 97 bool 98 needMoreBytes() 99 { 100 return true; 101 } 102 103 bool 104 instReady() 105 { 106 return instDone; 107 } 108 protected: 109 /// A cache of decoded instruction objects.
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108 static DecodeCache defaultCache;
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110 static GenericISA::BasicDecodeCache defaultCache; |
111 112 public: 113 StaticInstPtr decodeInst(ExtMachInst mach_inst); 114 115 /// Decode a machine instruction. 116 /// @param mach_inst The binary instruction to decode. 117 /// @retval A pointer to the corresponding StaticInst object. 118 StaticInstPtr 119 decode(ExtMachInst mach_inst, Addr addr) 120 { 121 return defaultCache.decode(this, mach_inst, addr); 122 } 123 124 StaticInstPtr 125 decode(PowerISA::PCState &nextPC) 126 { 127 if (!instDone) 128 return NULL; 129 instDone = false; 130 return decode(emi, nextPC.instAddr()); 131 } 132}; 133 134} // namespace PowerISA 135 136#endif // __ARCH_POWER_DECODER_HH__
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