1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Hansson
38 */
39
40#ifndef __ARCH_NULL_REGISTERS_HH__
41#define __ARCH_NULL_REGISTERS_HH__
42
43#include "arch/generic/vec_reg.hh"
44#include "arch/types.hh"
45#include "base/types.hh"
46
47namespace NullISA {
48
49typedef RegVal IntReg;
50typedef RegVal FloatRegBits;
51typedef uint8_t CCReg;
52typedef RegVal MiscReg;
53const RegIndex ZeroReg = 0;
54
55// dummy typedefs since we don't have vector regs
56constexpr unsigned NumVecElemPerVecReg = 2;
57using VecElem = uint32_t;
58using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
59using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
60using VecRegContainer = VecReg::Container;
61// This has to be one to prevent warnings that are treated as errors
62constexpr unsigned NumVecRegs = 1;
63
64}
65
66#endif // __ARCH_NULL_REGISTERS_HH__