vtophys.hh (8229:78bf55f23338) vtophys.hh (8730:0a742249f76b)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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33
34#ifndef __ARCH_MIPS_VTOPHYS_H__
35#define __ARCH_MIPS_VTOPHYS_H__
36
37#include "arch/mips/isa_traits.hh"
38#include "arch/mips/utility.hh"
39
40class ThreadContext;
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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33
34#ifndef __ARCH_MIPS_VTOPHYS_H__
35#define __ARCH_MIPS_VTOPHYS_H__
36
37#include "arch/mips/isa_traits.hh"
38#include "arch/mips/utility.hh"
39
40class ThreadContext;
41class FunctionalPort;
42
43namespace MipsISA {
44 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
45
46 // User Virtual
47 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
48
49 inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; }

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42namespace MipsISA {
43 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
44
45 // User Virtual
46 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
47
48 inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; }

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