vtophys.hh (5222:bb733a878f85) vtophys.hh (5254:c555f8b07345)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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29 * Steve Reinhardt
30 * Jaidev Patwardhan
31 */
32
33#ifndef __ARCH_MIPS_VTOPHYS_H__
34#define __ARCH_MIPS_VTOPHYS_H__
35
36#include "arch/mips/isa_traits.hh"
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 20 unchanged lines hidden (view full) ---

29 * Steve Reinhardt
30 * Jaidev Patwardhan
31 */
32
33#ifndef __ARCH_MIPS_VTOPHYS_H__
34#define __ARCH_MIPS_VTOPHYS_H__
35
36#include "arch/mips/isa_traits.hh"
37#include "arch/mips/pagetable.hh"
38#include "arch/mips/utility.hh"
39
40
41class ThreadContext;
42class FunctionalPort;
43
44namespace MipsISA {
37#include "arch/mips/utility.hh"
38
39
40class ThreadContext;
41class FunctionalPort;
42
43namespace MipsISA {
44 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
45
45
46 // User Virtual
47 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
46
48
49 inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; }
50
51 inline Addr KSeg02Phys(Addr addr) { return addr & KSeg0Mask; }
52
53 inline Addr KSeg12Phys(Addr addr) { return addr & KSeg1Mask; }
54
55 inline bool IsKSeg1(Addr a) { return KSeg1Base <= a && a <= KSeg1End; }
56
57 inline bool IsKSSeg(Addr a) { return KSSegBase <= a && a <= KSSegEnd; }
58
59 inline bool IsKSeg3(Addr a) { return KSeg3Base <= a && a <= KSeg3End; }
60
61
47 Addr vtophys(Addr vaddr);
48 Addr vtophys(ThreadContext *tc, Addr vaddr);
49
50};
51#endif // __ARCH_MIPS_VTOPHYS_H__
52
62 Addr vtophys(Addr vaddr);
63 Addr vtophys(ThreadContext *tc, Addr vaddr);
64
65};
66#endif // __ARCH_MIPS_VTOPHYS_H__
67