vtophys.hh (5268:5bfc53fe60e7) vtophys.hh (8229:78bf55f23338)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Ali Saidi
30 * Nathan Binkert
31 * Jaidev Patwardhan
32 */
33
34#ifndef __ARCH_MIPS_VTOPHYS_H__
35#define __ARCH_MIPS_VTOPHYS_H__
36
37#include "arch/mips/isa_traits.hh"
38#include "arch/mips/utility.hh"
39
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Ali Saidi
30 * Nathan Binkert
31 * Jaidev Patwardhan
32 */
33
34#ifndef __ARCH_MIPS_VTOPHYS_H__
35#define __ARCH_MIPS_VTOPHYS_H__
36
37#include "arch/mips/isa_traits.hh"
38#include "arch/mips/utility.hh"
39
40
41class ThreadContext;
42class FunctionalPort;
43
44namespace MipsISA {
45 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
46
47 // User Virtual
48 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
49
50 inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; }
51
52 inline Addr KSeg02Phys(Addr addr) { return addr & KSeg0Mask; }
53
54 inline Addr KSeg12Phys(Addr addr) { return addr & KSeg1Mask; }
55
56 inline bool IsKSeg1(Addr a) { return KSeg1Base <= a && a <= KSeg1End; }
57
58 inline bool IsKSSeg(Addr a) { return KSSegBase <= a && a <= KSSegEnd; }
59
60 inline bool IsKSeg3(Addr a) { return KSeg3Base <= a && a <= KSeg3End; }
61
62
63 Addr vtophys(Addr vaddr);
64 Addr vtophys(ThreadContext *tc, Addr vaddr);
65
66};
67#endif // __ARCH_MIPS_VTOPHYS_H__
68
40class ThreadContext;
41class FunctionalPort;
42
43namespace MipsISA {
44 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
45
46 // User Virtual
47 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
48
49 inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; }
50
51 inline Addr KSeg02Phys(Addr addr) { return addr & KSeg0Mask; }
52
53 inline Addr KSeg12Phys(Addr addr) { return addr & KSeg1Mask; }
54
55 inline bool IsKSeg1(Addr a) { return KSeg1Base <= a && a <= KSeg1End; }
56
57 inline bool IsKSSeg(Addr a) { return KSSegBase <= a && a <= KSSegEnd; }
58
59 inline bool IsKSeg3(Addr a) { return KSeg3Base <= a && a <= KSeg3End; }
60
61
62 Addr vtophys(Addr vaddr);
63 Addr vtophys(ThreadContext *tc, Addr vaddr);
64
65};
66#endif // __ARCH_MIPS_VTOPHYS_H__
67