vtophys.cc (6378:4a2ff62c3b4f) | vtophys.cc (8758:8c9bd68c5a55) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 23 unchanged lines hidden (view full) --- 32 */ 33 34#include <string> 35 36#include "arch/mips/vtophys.hh" 37#include "base/chunk_generator.hh" 38#include "base/trace.hh" 39#include "cpu/thread_context.hh" | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 23 unchanged lines hidden (view full) --- 32 */ 33 34#include <string> 35 36#include "arch/mips/vtophys.hh" 37#include "base/chunk_generator.hh" 38#include "base/trace.hh" 39#include "cpu/thread_context.hh" |
40#include "debug/VtoPhys.hh" |
|
40#include "mem/vport.hh" 41 42using namespace std; 43using namespace MipsISA; 44 45Addr 46MipsISA::vtophys(Addr vaddr) 47{ | 41#include "mem/vport.hh" 42 43using namespace std; 44using namespace MipsISA; 45 46Addr 47MipsISA::vtophys(Addr vaddr) 48{ |
48 Addr paddr = 0; 49 if (MipsISA::IsUSeg(vaddr)) 50 DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr); 51 else if (MipsISA::IsKSeg0(vaddr)) 52 paddr = MipsISA::KSeg02Phys(vaddr); 53 else if(MipsISA::IsKSeg1(vaddr)) 54 paddr = MipsISA::KSeg12Phys(vaddr); 55 else 56 panic("vtophys: ptbr is not set on " 57 "virtual lookup for vaddr %#x", vaddr); 58 59 DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); 60 61 return paddr; | 49 fatal("VTOPHYS: Unimplemented on MIPS\n"); 50 return 0; |
62} 63 64Addr 65MipsISA::vtophys(ThreadContext *tc, Addr addr) 66{ | 51} 52 53Addr 54MipsISA::vtophys(ThreadContext *tc, Addr addr) 55{ |
67 fatal("VTOPHYS: Unimplemented on MIPS\n"); | 56 fatal("VTOPHYS: Unimplemented on MIPS\n"); |
68} 69 | 57} 58 |