utility.hh (6329:5d8b91875859) | utility.hh (6378:4a2ff62c3b4f) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 31 unchanged lines hidden (view full) --- 40#include "base/types.hh" 41#include "config/full_system.hh" 42#include "cpu/thread_context.hh" 43 44class ThreadContext; 45 46namespace MipsISA { 47 | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 31 unchanged lines hidden (view full) --- 40#include "base/types.hh" 41#include "config/full_system.hh" 42#include "cpu/thread_context.hh" 43 44class ThreadContext; 45 46namespace MipsISA { 47 |
48 uint64_t getArgument(ThreadContext *tc, int number, bool fp); | 48uint64_t getArgument(ThreadContext *tc, int number, bool fp); |
49 | 49 |
50 //////////////////////////////////////////////////////////////////////// 51 // 52 // Floating Point Utility Functions 53 // 54 uint64_t fpConvert(ConvertType cvt_type, double fp_val); 55 double roundFP(double val, int digits); 56 double truncFP(double val); | 50//////////////////////////////////////////////////////////////////////// 51// 52// Floating Point Utility Functions 53// 54uint64_t fpConvert(ConvertType cvt_type, double fp_val); 55double roundFP(double val, int digits); 56double truncFP(double val); |
57 | 57 |
58 bool getCondCode(uint32_t fcsr, int cc); 59 uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); 60 uint32_t genInvalidVector(uint32_t fcsr); | 58bool getCondCode(uint32_t fcsr, int cc); 59uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); 60uint32_t genInvalidVector(uint32_t fcsr); |
61 | 61 |
62 bool isNan(void *val_ptr, int size); 63 bool isQnan(void *val_ptr, int size); 64 bool isSnan(void *val_ptr, int size); | 62bool isNan(void *val_ptr, int size); 63bool isQnan(void *val_ptr, int size); 64bool isSnan(void *val_ptr, int size); |
65 | 65 |
66 static inline bool 67 inUserMode(ThreadContext *tc) 68 { 69 MiscReg Stat = tc->readMiscReg(MipsISA::Status); 70 MiscReg Dbg = tc->readMiscReg(MipsISA::Debug); | 66static inline bool 67inUserMode(ThreadContext *tc) 68{ 69 MiscReg Stat = tc->readMiscReg(MipsISA::Status); 70 MiscReg Dbg = tc->readMiscReg(MipsISA::Debug); |
71 | 71 |
72 if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible 73 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible 74 && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode 75 // Unable to use Status_CU0, etc directly, using bitfields & masks 76 return true; 77 } else { 78 return false; 79 } | 72 if ((Stat & 0x10000006) == 0 && // EXL, ERL or CU0 set, CP0 accessible 73 (Dbg & 0x40000000) == 0 && // DM bit set, CP0 accessible 74 (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode 75 // Unable to use Status_CU0, etc directly, using bitfields & masks 76 return true; 77 } else { 78 return false; |
80 } | 79 } |
80} |
|
81 | 81 |
82 // Instruction address compression hooks 83 static inline Addr realPCToFetchPC(const Addr &addr) { 84 return addr; 85 } | 82// Instruction address compression hooks 83static inline Addr realPCToFetchPC(const Addr &addr) { 84 return addr; 85} |
86 | 86 |
87 static inline Addr fetchPCToRealPC(const Addr &addr) { 88 return addr; 89 } | 87static inline Addr fetchPCToRealPC(const Addr &addr) { 88 return addr; 89} |
90 | 90 |
91 // the size of "fetched" instructions (not necessarily the size 92 // of real instructions for PISA) 93 static inline size_t fetchInstSize() { 94 return sizeof(MachInst); 95 } | 91// the size of "fetched" instructions (not necessarily the size 92// of real instructions for PISA) 93static inline size_t fetchInstSize() { 94 return sizeof(MachInst); 95} |
96 | 96 |
97 //////////////////////////////////////////////////////////////////////// 98 // 99 // Register File Utility Functions 100 // 101 static inline MachInst makeRegisterCopy(int dest, int src) { 102 panic("makeRegisterCopy not implemented"); 103 return 0; 104 } | 97//////////////////////////////////////////////////////////////////////// 98// 99// Register File Utility Functions 100// 101static inline MachInst makeRegisterCopy(int dest, int src) { 102 panic("makeRegisterCopy not implemented"); 103 return 0; 104} |
105 | 105 |
106 template <class CPU> 107 void zeroRegisters(CPU *cpu); | 106template 107void zeroRegisters(CPU *cpu); |
108 | 108 |
109 //////////////////////////////////////////////////////////////////////// 110 // 111 // Translation stuff 112 // 113 inline Addr 114 TruncPage(Addr addr) 115 { return addr & ~(PageBytes - 1); } | 109//////////////////////////////////////////////////////////////////////// 110// 111// Translation stuff 112// 113inline Addr 114TruncPage(Addr addr) 115{ return addr & ~(PageBytes - 1); } |
116 | 116 |
117 inline Addr 118 RoundPage(Addr addr) 119 { return (addr + PageBytes - 1) & ~(PageBytes - 1); } | 117inline Addr 118RoundPage(Addr addr) 119{ return (addr + PageBytes - 1) & ~(PageBytes - 1); } |
120 | 120 |
121 //////////////////////////////////////////////////////////////////////// 122 // 123 // CPU Utility 124 // 125 void startupCPU(ThreadContext *tc, int cpuId); | 121//////////////////////////////////////////////////////////////////////// 122// 123// CPU Utility 124// 125void startupCPU(ThreadContext *tc, int cpuId); |
126 | 126 |
127 void copyRegs(ThreadContext *src, ThreadContext *dest); 128 void copyMiscRegs(ThreadContext *src, ThreadContext *dest); | 127void copyRegs(ThreadContext *src, ThreadContext *dest); 128void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 129 |
129}; 130 131 132#endif | 130}; 131 132 133#endif |