utility.hh (4846:1811b9542646) | utility.hh (5222:bb733a878f85) |
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1/* | 1/* |
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. | 2 * Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved |
5 * | 3 * |
6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. | 4 * This software is part of the M5 simulator. |
16 * | 5 * |
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 6 * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 7 * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 8 * TO THESE TERMS AND CONDITIONS. |
28 * | 9 * |
29 * Authors: Nathan Binkert 30 * Steve Reinhardt 31 * Korey Sewell | 10 * Permission is granted to use, copy, create derivative works and 11 * distribute this software and such derivative works for any purpose, 12 * so long as (1) the copyright notice above, this grant of permission, 13 * and the disclaimer below appear in all copies and derivative works 14 * made, (2) the copyright notice above is augmented as appropriate to 15 * reflect the addition of any new copyrightable work in a derivative 16 * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3) 17 * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any 18 * advertising or publicity pertaining to the use or distribution of 19 * this software without specific, written prior authorization. 20 * 21 * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND 22 * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 23 * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 25 * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 26 * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 27 * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 28 * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 29 * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 30 * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 31 * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 32 * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 33 * 34 * Authors: Korey L. Sewell |
32 */ 33 34#ifndef __ARCH_MIPS_UTILITY_HH__ 35#define __ARCH_MIPS_UTILITY_HH__ | 35 */ 36 37#ifndef __ARCH_MIPS_UTILITY_HH__ 38#define __ARCH_MIPS_UTILITY_HH__ |
36 | 39#include "config/full_system.hh" |
37#include "arch/mips/types.hh" 38#include "arch/mips/isa_traits.hh" 39#include "base/misc.hh" 40#include "config/full_system.hh" 41//XXX This is needed for size_t. We should use something other than size_t 42//#include "kern/linux/linux.hh" 43#include "sim/host.hh" 44 45#include "cpu/thread_context.hh" 46 47class ThreadContext; 48 49namespace MipsISA { 50 | 40#include "arch/mips/types.hh" 41#include "arch/mips/isa_traits.hh" 42#include "base/misc.hh" 43#include "config/full_system.hh" 44//XXX This is needed for size_t. We should use something other than size_t 45//#include "kern/linux/linux.hh" 46#include "sim/host.hh" 47 48#include "cpu/thread_context.hh" 49 50class ThreadContext; 51 52namespace MipsISA { 53 |
51 inline uint64_t 52 getArgument(ThreadContext *tc, bool fp) 53 { 54 panic("getArgument() not implemented for MIPS\n"); 55 } | 54 uint64_t getArgument(ThreadContext *tc, int number, bool fp); |
56 57 //Floating Point Utility Functions 58 uint64_t fpConvert(ConvertType cvt_type, double fp_val); 59 double roundFP(double val, int digits); 60 double truncFP(double val); 61 62 bool getCondCode(uint32_t fcsr, int cc); 63 uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); 64 uint32_t genInvalidVector(uint32_t fcsr); 65 66 bool isNan(void *val_ptr, int size); 67 bool isQnan(void *val_ptr, int size); 68 bool isSnan(void *val_ptr, int size); 69 | 55 56 //Floating Point Utility Functions 57 uint64_t fpConvert(ConvertType cvt_type, double fp_val); 58 double roundFP(double val, int digits); 59 double truncFP(double val); 60 61 bool getCondCode(uint32_t fcsr, int cc); 62 uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); 63 uint32_t genInvalidVector(uint32_t fcsr); 64 65 bool isNan(void *val_ptr, int size); 66 bool isQnan(void *val_ptr, int size); 67 bool isSnan(void *val_ptr, int size); 68 |
70 /** 71 * Function to insure ISA semantics about 0 registers. 72 * @param tc The thread context. 73 */ 74 template <class TC> 75 void zeroRegisters(TC *tc); 76 | |
77 void startupCPU(ThreadContext *tc, int cpuId); 78 | 69 void startupCPU(ThreadContext *tc, int cpuId); 70 |
71 static inline bool 72 inUserMode(ThreadContext *tc) 73 { 74 MiscReg Stat = tc->readMiscReg(MipsISA::Status); 75 MiscReg Dbg = tc->readMiscReg(MipsISA::Debug); 76 77 if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible 78 && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible 79 && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode 80 // Unable to use Status_CU0, etc directly, using bitfields & masks 81 return true; 82 } else { 83 return false; 84 } 85 } 86 |
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79 // Instruction address compression hooks 80 static inline Addr realPCToFetchPC(const Addr &addr) { 81 return addr; 82 } 83 84 static inline Addr fetchPCToRealPC(const Addr &addr) { 85 return addr; 86 } --- 4 unchanged lines hidden (view full) --- 91 return sizeof(MachInst); 92 } 93 94 static inline MachInst makeRegisterCopy(int dest, int src) { 95 panic("makeRegisterCopy not implemented"); 96 return 0; 97 } 98 | 87 // Instruction address compression hooks 88 static inline Addr realPCToFetchPC(const Addr &addr) { 89 return addr; 90 } 91 92 static inline Addr fetchPCToRealPC(const Addr &addr) { 93 return addr; 94 } --- 4 unchanged lines hidden (view full) --- 99 return sizeof(MachInst); 100 } 101 102 static inline MachInst makeRegisterCopy(int dest, int src) { 103 panic("makeRegisterCopy not implemented"); 104 return 0; 105 } 106 |
99 static inline ExtMachInst 100 makeExtMI(MachInst inst, ThreadContext * xc) { 101#if FULL_SYSTEM 102 ExtMachInst ext_inst = inst; 103 if (xc->readPC() && 0x1) 104 return ext_inst|=(static_cast<ExtMachInst>(xc->readPC() & 0x1) << 32); 105 else 106 return ext_inst; 107#else 108 return ExtMachInst(inst); 109#endif | 107 static inline int flattenFloatIndex(ThreadContext * tc, int reg) 108 { 109 return reg; |
110 } | 110 } |
111 112 int flattenIntIndex(ThreadContext * tc, int reg); 113 114 void copyRegs(ThreadContext *src, ThreadContext *dest); 115 116 void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 117 118 119 template <class CPU> 120 void zeroRegisters(CPU *cpu); 121 122 //////////////////////////////////////////////////////////////////////// 123 // 124 // Translation stuff 125 // 126 127 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 128 129 // User Virtual 130 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } 131 132 inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; } 133 134 inline Addr KSeg02Phys(Addr addr) { return addr & KSeg0Mask; } 135 136 inline Addr KSeg12Phys(Addr addr) { return addr & KSeg1Mask; } 137 138 inline bool IsKSeg1(Addr a) { return KSeg1Base <= a && a <= KSeg1End; } 139 140 inline bool IsKSSeg(Addr a) { return KSSegBase <= a && a <= KSSegEnd; } 141 142 inline bool IsKSeg3(Addr a) { return KSeg3Base <= a && a <= KSeg3End; } 143 144 inline Addr 145 TruncPage(Addr addr) 146 { return addr & ~(PageBytes - 1); } 147 148 inline Addr 149 RoundPage(Addr addr) 150 { return (addr + PageBytes - 1) & ~(PageBytes - 1); } 151 152 void initCPU(ThreadContext *tc, int cpuId); 153 void initIPRs(ThreadContext *tc, int cpuId); 154 155 /** 156 * Function to check for and process any interrupts. 157 * @param tc The thread context. 158 */ 159 template <class TC> 160 void processInterrupts(TC *tc); 161 |
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111}; 112 113 114#endif | 162}; 163 164 165#endif |