1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright --- 34 unchanged lines hidden (view full) --- 43#include "sim/host.hh" 44 45#include "cpu/thread_context.hh" 46 47class ThreadContext; 48 49namespace MipsISA { 50 |
51 //Floating Point Utility Functions 52 uint64_t fpConvert(ConvertType cvt_type, double fp_val); 53 double roundFP(double val, int digits); 54 double truncFP(double val); 55 56 bool getCondCode(uint32_t fcsr, int cc); 57 uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); 58 uint32_t genInvalidVector(uint32_t fcsr); --- 6 unchanged lines hidden (view full) --- 65 * Function to insure ISA semantics about 0 registers. 66 * @param tc The thread context. 67 */ 68 template <class TC> 69 void zeroRegisters(TC *tc); 70 71 void startupCPU(ThreadContext *tc, int cpuId); 72 |
73 // Instruction address compression hooks 74 static inline Addr realPCToFetchPC(const Addr &addr) { 75 return addr; 76 } 77 78 static inline Addr fetchPCToRealPC(const Addr &addr) { 79 return addr; 80 } --- 28 unchanged lines hidden --- |