1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Nathan Binkert
30 * Steve Reinhardt
31 * Korey Sewell
32 */
33
34#ifndef __ARCH_MIPS_UTILITY_HH__
35#define __ARCH_MIPS_UTILITY_HH__
36#include "config/full_system.hh"
37#include "arch/mips/types.hh"
38#include "arch/mips/isa_traits.hh"
39#include "base/misc.hh"
40#include "base/types.hh"
41#include "config/full_system.hh"
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Nathan Binkert
30 * Steve Reinhardt
31 * Korey Sewell
32 */
33
34#ifndef __ARCH_MIPS_UTILITY_HH__
35#define __ARCH_MIPS_UTILITY_HH__
36#include "config/full_system.hh"
37#include "arch/mips/types.hh"
38#include "arch/mips/isa_traits.hh"
39#include "base/misc.hh"
40#include "base/types.hh"
41#include "config/full_system.hh"
|
| 42#include "cpu/static_inst.hh"
|
42#include "cpu/thread_context.hh"
43
44class ThreadContext;
45
46namespace MipsISA {
47
| 43#include "cpu/thread_context.hh"
44
45class ThreadContext;
46
47namespace MipsISA {
48
|
| 49inline PCState
50buildRetPC(const PCState &curPC, const PCState &callPC)
51{
52 PCState ret = callPC;
53 ret.advance();
54 ret.pc(curPC.npc());
55 return ret;
56}
57
|
48uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
49
50////////////////////////////////////////////////////////////////////////
51//
52// Floating Point Utility Functions
53//
54uint64_t fpConvert(ConvertType cvt_type, double fp_val);
55double roundFP(double val, int digits);
56double truncFP(double val);
57
58bool getCondCode(uint32_t fcsr, int cc);
59uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val);
60uint32_t genInvalidVector(uint32_t fcsr);
61
62bool isNan(void *val_ptr, int size);
63bool isQnan(void *val_ptr, int size);
64bool isSnan(void *val_ptr, int size);
65
66static inline bool
67inUserMode(ThreadContext *tc)
68{
69 MiscReg Stat = tc->readMiscReg(MISCREG_STATUS);
70 MiscReg Dbg = tc->readMiscReg(MISCREG_DEBUG);
71
72 if ((Stat & 0x10000006) == 0 && // EXL, ERL or CU0 set, CP0 accessible
73 (Dbg & 0x40000000) == 0 && // DM bit set, CP0 accessible
74 (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
75 // Unable to use Status_CU0, etc directly, using bitfields & masks
76 return true;
77 } else {
78 return false;
79 }
80}
81
82template <class CPU>
83void zeroRegisters(CPU *cpu);
84
85////////////////////////////////////////////////////////////////////////
86//
87// Translation stuff
88//
89inline Addr
90TruncPage(Addr addr)
91{ return addr & ~(PageBytes - 1); }
92
93inline Addr
94RoundPage(Addr addr)
95{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
96
97////////////////////////////////////////////////////////////////////////
98//
99// CPU Utility
100//
101void startupCPU(ThreadContext *tc, int cpuId);
102
103void copyRegs(ThreadContext *src, ThreadContext *dest);
104void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
105
106void skipFunction(ThreadContext *tc);
107
| 58uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
59
60////////////////////////////////////////////////////////////////////////
61//
62// Floating Point Utility Functions
63//
64uint64_t fpConvert(ConvertType cvt_type, double fp_val);
65double roundFP(double val, int digits);
66double truncFP(double val);
67
68bool getCondCode(uint32_t fcsr, int cc);
69uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val);
70uint32_t genInvalidVector(uint32_t fcsr);
71
72bool isNan(void *val_ptr, int size);
73bool isQnan(void *val_ptr, int size);
74bool isSnan(void *val_ptr, int size);
75
76static inline bool
77inUserMode(ThreadContext *tc)
78{
79 MiscReg Stat = tc->readMiscReg(MISCREG_STATUS);
80 MiscReg Dbg = tc->readMiscReg(MISCREG_DEBUG);
81
82 if ((Stat & 0x10000006) == 0 && // EXL, ERL or CU0 set, CP0 accessible
83 (Dbg & 0x40000000) == 0 && // DM bit set, CP0 accessible
84 (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
85 // Unable to use Status_CU0, etc directly, using bitfields & masks
86 return true;
87 } else {
88 return false;
89 }
90}
91
92template <class CPU>
93void zeroRegisters(CPU *cpu);
94
95////////////////////////////////////////////////////////////////////////
96//
97// Translation stuff
98//
99inline Addr
100TruncPage(Addr addr)
101{ return addr & ~(PageBytes - 1); }
102
103inline Addr
104RoundPage(Addr addr)
105{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
106
107////////////////////////////////////////////////////////////////////////
108//
109// CPU Utility
110//
111void startupCPU(ThreadContext *tc, int cpuId);
112
113void copyRegs(ThreadContext *src, ThreadContext *dest);
114void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
115
116void skipFunction(ThreadContext *tc);
117
|
| 118inline void
119advancePC(PCState &pc, const StaticInstPtr inst)
120{
121 pc.advance();
122}
123
|
108};
109
110
111#endif
| 124};
125
126
127#endif
|