utility.hh (3120:e49afeaf79e9) | utility.hh (4181:6edaeff44647) |
---|---|
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan |
3 * Copyright (c) 2007 MIPS Technologies, Inc. |
|
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the --- 11 unchanged lines hidden (view full) --- 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt | 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the --- 11 unchanged lines hidden (view full) --- 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Nathan Binkert 30 * Steve Reinhardt |
31 * Korey Sewell |
|
30 */ 31 32#ifndef __ARCH_MIPS_UTILITY_HH__ 33#define __ARCH_MIPS_UTILITY_HH__ 34 35#include "arch/mips/types.hh" 36#include "base/misc.hh" 37#include "config/full_system.hh" --- 43 unchanged lines hidden (view full) --- 81 return sizeof(MachInst); 82 } 83 84 static inline MachInst makeRegisterCopy(int dest, int src) { 85 panic("makeRegisterCopy not implemented"); 86 return 0; 87 } 88 | 32 */ 33 34#ifndef __ARCH_MIPS_UTILITY_HH__ 35#define __ARCH_MIPS_UTILITY_HH__ 36 37#include "arch/mips/types.hh" 38#include "base/misc.hh" 39#include "config/full_system.hh" --- 43 unchanged lines hidden (view full) --- 83 return sizeof(MachInst); 84 } 85 86 static inline MachInst makeRegisterCopy(int dest, int src) { 87 panic("makeRegisterCopy not implemented"); 88 return 0; 89 } 90 |
89 static inline ExtMachInst 90 makeExtMI(MachInst inst, ThreadContext * xc) { 91#if FULL_SYSTEM 92 ExtMachInst ext_inst = inst; 93 if (xc->readPC() && 0x1) 94 return ext_inst|=(static_cast<ExtMachInst>(xc->readPC() & 0x1) << 32); 95 else 96 return ext_inst; 97#else 98 return ExtMachInst(inst); 99#endif | 91 enum PredecodeResult { 92 MoreBytes = 1, 93 ExtMIReady = 2 94 }; 95 96 static inline unsigned int 97 predecode(ExtMachInst &emi, Addr, MachInst inst, ThreadContext *) { 98 emi = inst; 99 return MoreBytes | ExtMIReady; |
100 } 101}; 102 103 104#endif | 100 } 101}; 102 103 104#endif |