utility.cc (4661:44458219add1) utility.cc (5222:bb733a878f85)
1/*
1/*
2 * Copyright (c) 2003-2006 The Regents of The University of Michigan
3 * All rights reserved.
2 * Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
4 *
3 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
4 * This software is part of the M5 simulator.
15 *
5 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6 * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
7 * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
8 * TO THESE TERMS AND CONDITIONS.
27 *
9 *
28 * Authors: Korey Sewell
10 * Permission is granted to use, copy, create derivative works and
11 * distribute this software and such derivative works for any purpose,
12 * so long as (1) the copyright notice above, this grant of permission,
13 * and the disclaimer below appear in all copies and derivative works
14 * made, (2) the copyright notice above is augmented as appropriate to
15 * reflect the addition of any new copyrightable work in a derivative
16 * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
17 * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
18 * advertising or publicity pertaining to the use or distribution of
19 * this software without specific, written prior authorization.
20 *
21 * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND
22 * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
23 * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
25 * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
26 * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
27 * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
28 * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
29 * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
30 * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
31 * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
32 * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
33 *
34 * Authors: Korey L. Sewell
29 */
30
31#include "arch/mips/isa_traits.hh"
32#include "arch/mips/utility.hh"
35 */
36
37#include "arch/mips/isa_traits.hh"
38#include "arch/mips/utility.hh"
33#include "arch/mips/constants.hh"
34#include "config/full_system.hh"
35#include "cpu/thread_context.hh"
36#include "cpu/static_inst.hh"
37#include "sim/serialize.hh"
38#include "base/bitfield.hh"
39#include "base/misc.hh"
40
39#include "config/full_system.hh"
40#include "cpu/thread_context.hh"
41#include "cpu/static_inst.hh"
42#include "sim/serialize.hh"
43#include "base/bitfield.hh"
44#include "base/misc.hh"
45
46#if FULL_SYSTEM
47#include "arch/mips/vtophys.hh"
48#include "mem/vport.hh"
49#endif
50
51
41using namespace MipsISA;
42using namespace std;
43
52using namespace MipsISA;
53using namespace std;
54
55namespace MipsISA {
56
44uint64_t
57uint64_t
45MipsISA::fpConvert(ConvertType cvt_type, double fp_val)
58getArgument(ThreadContext *tc, int number, bool fp)
46{
59{
60#if FULL_SYSTEM
61 if (number < NumArgumentRegs) {
62 if (fp)
63 return tc->readFloatRegBits(ArgumentReg[number]);
64 else
65 return tc->readIntReg(ArgumentReg[number]);
66 } else {
67 Addr sp = tc->readIntReg(StackPointerReg);
68 VirtualPort *vp = tc->getVirtPort(tc);
69 uint64_t arg = vp->read<uint64_t>(sp +
70 (number-NumArgumentRegs) * sizeof(uint64_t));
71 tc->delVirtPort(vp);
72 return arg;
73 }
74#else
75 panic("getArgument() is Full system only\n");
76 M5_DUMMY_RETURN
77#endif
78}
47
79
80uint64_t
81fpConvert(ConvertType cvt_type, double fp_val)
82{
83
48 switch (cvt_type)
49 {
50 case SINGLE_TO_DOUBLE:
51 {
52 double sdouble_val = fp_val;
53 void *sdouble_ptr = &sdouble_val;
54 uint64_t sdp_bits = *(uint64_t *) sdouble_ptr;
55 return sdp_bits;

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81
82 default:
83 panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type);
84 return 0;
85 }
86}
87
88double
84 switch (cvt_type)
85 {
86 case SINGLE_TO_DOUBLE:
87 {
88 double sdouble_val = fp_val;
89 void *sdouble_ptr = &sdouble_val;
90 uint64_t sdp_bits = *(uint64_t *) sdouble_ptr;
91 return sdp_bits;

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117
118 default:
119 panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type);
120 return 0;
121 }
122}
123
124double
89MipsISA::roundFP(double val, int digits)
125roundFP(double val, int digits)
90{
91 double digit_offset = pow(10.0,digits);
92 val = val * digit_offset;
93 val = val + 0.5;
94 val = floor(val);
95 val = val / digit_offset;
96 return val;
97}
98
99double
126{
127 double digit_offset = pow(10.0,digits);
128 val = val * digit_offset;
129 val = val + 0.5;
130 val = floor(val);
131 val = val / digit_offset;
132 return val;
133}
134
135double
100MipsISA::truncFP(double val)
136truncFP(double val)
101{
102 int trunc_val = (int) val;
103 return (double) trunc_val;
104}
105
106bool
137{
138 int trunc_val = (int) val;
139 return (double) trunc_val;
140}
141
142bool
107MipsISA::getCondCode(uint32_t fcsr, int cc_idx)
143getCondCode(uint32_t fcsr, int cc_idx)
108{
109 int shift = (cc_idx == 0) ? 23 : cc_idx + 24;
110 bool cc_val = (fcsr >> shift) & 0x00000001;
111 return cc_val;
112}
113
114uint32_t
144{
145 int shift = (cc_idx == 0) ? 23 : cc_idx + 24;
146 bool cc_val = (fcsr >> shift) & 0x00000001;
147 return cc_val;
148}
149
150uint32_t
115MipsISA::genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
151genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
116{
117 int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
118
119 fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 |
120 cc_val << cc_idx |
121 bits(fcsr, cc_idx - 1, 0);
122
123 return fcsr;
124}
125
126uint32_t
152{
153 int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
154
155 fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 |
156 cc_val << cc_idx |
157 bits(fcsr, cc_idx - 1, 0);
158
159 return fcsr;
160}
161
162uint32_t
127MipsISA::genInvalidVector(uint32_t fcsr_bits)
163genInvalidVector(uint32_t fcsr_bits)
128{
129 //Set FCSR invalid in "flag" field
130 int invalid_offset = Invalid + Flag_Field;
131 fcsr_bits = fcsr_bits | (1 << invalid_offset);
132
133 //Set FCSR invalid in "cause" flag
134 int cause_offset = Invalid + Cause_Field;
135 fcsr_bits = fcsr_bits | (1 << cause_offset);
136
137 return fcsr_bits;
138}
139
140bool
164{
165 //Set FCSR invalid in "flag" field
166 int invalid_offset = Invalid + Flag_Field;
167 fcsr_bits = fcsr_bits | (1 << invalid_offset);
168
169 //Set FCSR invalid in "cause" flag
170 int cause_offset = Invalid + Cause_Field;
171 fcsr_bits = fcsr_bits | (1 << cause_offset);
172
173 return fcsr_bits;
174}
175
176bool
141MipsISA::isNan(void *val_ptr, int size)
177isNan(void *val_ptr, int size)
142{
143 switch (size)
144 {
145 case 32:
146 {
147 uint32_t val_bits = *(uint32_t *) val_ptr;
148 return (bits(val_bits, 30, 23) == 0xFF);
149 }

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156
157 default:
158 panic("Type unsupported. Size mismatch\n");
159 }
160}
161
162
163bool
178{
179 switch (size)
180 {
181 case 32:
182 {
183 uint32_t val_bits = *(uint32_t *) val_ptr;
184 return (bits(val_bits, 30, 23) == 0xFF);
185 }

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192
193 default:
194 panic("Type unsupported. Size mismatch\n");
195 }
196}
197
198
199bool
164MipsISA::isQnan(void *val_ptr, int size)
200isQnan(void *val_ptr, int size)
165{
166 switch (size)
167 {
168 case 32:
169 {
170 uint32_t val_bits = *(uint32_t *) val_ptr;
171 return (bits(val_bits, 30, 22) == 0x1FE);
172 }

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178 }
179
180 default:
181 panic("Type unsupported. Size mismatch\n");
182 }
183}
184
185bool
201{
202 switch (size)
203 {
204 case 32:
205 {
206 uint32_t val_bits = *(uint32_t *) val_ptr;
207 return (bits(val_bits, 30, 22) == 0x1FE);
208 }

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214 }
215
216 default:
217 panic("Type unsupported. Size mismatch\n");
218 }
219}
220
221bool
186MipsISA::isSnan(void *val_ptr, int size)
222isSnan(void *val_ptr, int size)
187{
188 switch (size)
189 {
190 case 32:
191 {
192 uint32_t val_bits = *(uint32_t *) val_ptr;
193 return (bits(val_bits, 30, 22) == 0x1FF);
194 }

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199 return (bits(val_bits, 62, 51) == 0xFFF);
200 }
201
202 default:
203 panic("Type unsupported. Size mismatch\n");
204 }
205}
206
223{
224 switch (size)
225 {
226 case 32:
227 {
228 uint32_t val_bits = *(uint32_t *) val_ptr;
229 return (bits(val_bits, 30, 22) == 0x1FF);
230 }

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235 return (bits(val_bits, 62, 51) == 0xFFF);
236 }
237
238 default:
239 panic("Type unsupported. Size mismatch\n");
240 }
241}
242
243int
244flattenIntIndex(ThreadContext * tc, int reg)
245{
246 return reg;
247}
248
249
207void
250void
208MipsISA::startupCPU(ThreadContext *tc, int cpuId)
251copyRegs(ThreadContext *src, ThreadContext *dest)
209{
252{
210 tc->activate(0);
253 panic("Copy Regs Not Implemented Yet\n");
211}
254}
255
256void
257copyMiscRegs(ThreadContext *src, ThreadContext *dest)
258{
259 panic("Copy Misc. Regs Not Implemented Yet\n");
260}
261
262template <class CPU>
263void
264zeroRegisters(CPU *cpu)
265{
266 // Insure ISA semantics
267 // (no longer very clean due to the change in setIntReg() in the
268 // cpu model. Consider changing later.)
269 cpu->thread->setIntReg(ZeroReg, 0);
270 cpu->thread->setFloatReg(ZeroReg, 0.0);
271}
272
273void
274startupCPU(ThreadContext *tc, int cpuId)
275{
276 tc->activate(0/*tc->getThreadNum()*/);
277}
278
279} // namespace MipsISA