1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#include <cmath>
32
33#include "arch/mips/isa_traits.hh"
| 1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#include <cmath>
32
33#include "arch/mips/isa_traits.hh"
|
46using namespace MipsISA;
47using namespace std;
48
49namespace MipsISA {
50
51uint64_t
52getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
53{
54 panic("getArgument() not implemented\n");
55 M5_DUMMY_RETURN
56}
57
58uint64_t
59fpConvert(ConvertType cvt_type, double fp_val)
60{
61
62 switch (cvt_type)
63 {
64 case SINGLE_TO_DOUBLE:
65 {
66 double sdouble_val = fp_val;
67 void *sdouble_ptr = &sdouble_val;
68 uint64_t sdp_bits = *(uint64_t *) sdouble_ptr;
69 return sdp_bits;
70 }
71
72 case SINGLE_TO_WORD:
73 {
74 int32_t sword_val = (int32_t) fp_val;
75 void *sword_ptr = &sword_val;
76 uint64_t sword_bits= *(uint32_t *) sword_ptr;
77 return sword_bits;
78 }
79
80 case WORD_TO_SINGLE:
81 {
82 float wfloat_val = fp_val;
83 void *wfloat_ptr = &wfloat_val;
84 uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr;
85 return wfloat_bits;
86 }
87
88 case WORD_TO_DOUBLE:
89 {
90 double wdouble_val = fp_val;
91 void *wdouble_ptr = &wdouble_val;
92 uint64_t wdp_bits = *(uint64_t *) wdouble_ptr;
93 return wdp_bits;
94 }
95
96 default:
97 panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type);
98 return 0;
99 }
100}
101
102double
103roundFP(double val, int digits)
104{
105 double digit_offset = pow(10.0,digits);
106 val = val * digit_offset;
107 val = val + 0.5;
108 val = floor(val);
109 val = val / digit_offset;
110 return val;
111}
112
113double
114truncFP(double val)
115{
116 int trunc_val = (int) val;
117 return (double) trunc_val;
118}
119
120bool
121getCondCode(uint32_t fcsr, int cc_idx)
122{
123 int shift = (cc_idx == 0) ? 23 : cc_idx + 24;
124 bool cc_val = (fcsr >> shift) & 0x00000001;
125 return cc_val;
126}
127
128uint32_t
129genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
130{
131 int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
132
133 fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
134 cc_val << cc_idx |
135 bits(fcsr, cc_idx - 1, 0);
136
137 return fcsr;
138}
139
140uint32_t
141genInvalidVector(uint32_t fcsr_bits)
142{
143 //Set FCSR invalid in "flag" field
144 int invalid_offset = Invalid + Flag_Field;
145 fcsr_bits = fcsr_bits | (1 << invalid_offset);
146
147 //Set FCSR invalid in "cause" flag
148 int cause_offset = Invalid + Cause_Field;
149 fcsr_bits = fcsr_bits | (1 << cause_offset);
150
151 return fcsr_bits;
152}
153
154bool
155isNan(void *val_ptr, int size)
156{
157 switch (size)
158 {
159 case 32:
160 {
161 uint32_t val_bits = *(uint32_t *) val_ptr;
162 return (bits(val_bits, 30, 23) == 0xFF);
163 }
164
165 case 64:
166 {
167 uint64_t val_bits = *(uint64_t *) val_ptr;
168 return (bits(val_bits, 62, 52) == 0x7FF);
169 }
170
171 default:
172 panic("Type unsupported. Size mismatch\n");
173 }
174}
175
176
177bool
178isQnan(void *val_ptr, int size)
179{
180 switch (size)
181 {
182 case 32:
183 {
184 uint32_t val_bits = *(uint32_t *) val_ptr;
185 return (bits(val_bits, 30, 22) == 0x1FE);
186 }
187
188 case 64:
189 {
190 uint64_t val_bits = *(uint64_t *) val_ptr;
191 return (bits(val_bits, 62, 51) == 0xFFE);
192 }
193
194 default:
195 panic("Type unsupported. Size mismatch\n");
196 }
197}
198
199bool
200isSnan(void *val_ptr, int size)
201{
202 switch (size)
203 {
204 case 32:
205 {
206 uint32_t val_bits = *(uint32_t *) val_ptr;
207 return (bits(val_bits, 30, 22) == 0x1FF);
208 }
209
210 case 64:
211 {
212 uint64_t val_bits = *(uint64_t *) val_ptr;
213 return (bits(val_bits, 62, 51) == 0xFFF);
214 }
215
216 default:
217 panic("Type unsupported. Size mismatch\n");
218 }
219}
220
221template <class CPU>
222void
223zeroRegisters(CPU *cpu)
224{
225 // Insure ISA semantics
226 // (no longer very clean due to the change in setIntReg() in the
227 // cpu model. Consider changing later.)
228 cpu->thread->setIntReg(ZeroReg, 0);
229 cpu->thread->setFloatReg(ZeroReg, 0.0);
230}
231
232void
233startupCPU(ThreadContext *tc, int cpuId)
234{
235 tc->activate(0/*tc->threadId()*/);
236}
237
238void
239initCPU(ThreadContext *tc, int cpuId)
240{}
241
242void
243copyRegs(ThreadContext *src, ThreadContext *dest)
244{
245 panic("Copy Regs Not Implemented Yet\n");
246}
247
248void
249copyMiscRegs(ThreadContext *src, ThreadContext *dest)
250{
251 panic("Copy Misc. Regs Not Implemented Yet\n");
252}
253void
254skipFunction(ThreadContext *tc)
255{
256 TheISA::PCState newPC = tc->pcState();
257 newPC.set(tc->readIntReg(ReturnAddressReg));
258 tc->pcState(newPC);
259}
260
261
262} // namespace MipsISA
| 45using namespace MipsISA;
46using namespace std;
47
48namespace MipsISA {
49
50uint64_t
51getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
52{
53 panic("getArgument() not implemented\n");
54 M5_DUMMY_RETURN
55}
56
57uint64_t
58fpConvert(ConvertType cvt_type, double fp_val)
59{
60
61 switch (cvt_type)
62 {
63 case SINGLE_TO_DOUBLE:
64 {
65 double sdouble_val = fp_val;
66 void *sdouble_ptr = &sdouble_val;
67 uint64_t sdp_bits = *(uint64_t *) sdouble_ptr;
68 return sdp_bits;
69 }
70
71 case SINGLE_TO_WORD:
72 {
73 int32_t sword_val = (int32_t) fp_val;
74 void *sword_ptr = &sword_val;
75 uint64_t sword_bits= *(uint32_t *) sword_ptr;
76 return sword_bits;
77 }
78
79 case WORD_TO_SINGLE:
80 {
81 float wfloat_val = fp_val;
82 void *wfloat_ptr = &wfloat_val;
83 uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr;
84 return wfloat_bits;
85 }
86
87 case WORD_TO_DOUBLE:
88 {
89 double wdouble_val = fp_val;
90 void *wdouble_ptr = &wdouble_val;
91 uint64_t wdp_bits = *(uint64_t *) wdouble_ptr;
92 return wdp_bits;
93 }
94
95 default:
96 panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type);
97 return 0;
98 }
99}
100
101double
102roundFP(double val, int digits)
103{
104 double digit_offset = pow(10.0,digits);
105 val = val * digit_offset;
106 val = val + 0.5;
107 val = floor(val);
108 val = val / digit_offset;
109 return val;
110}
111
112double
113truncFP(double val)
114{
115 int trunc_val = (int) val;
116 return (double) trunc_val;
117}
118
119bool
120getCondCode(uint32_t fcsr, int cc_idx)
121{
122 int shift = (cc_idx == 0) ? 23 : cc_idx + 24;
123 bool cc_val = (fcsr >> shift) & 0x00000001;
124 return cc_val;
125}
126
127uint32_t
128genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
129{
130 int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
131
132 fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
133 cc_val << cc_idx |
134 bits(fcsr, cc_idx - 1, 0);
135
136 return fcsr;
137}
138
139uint32_t
140genInvalidVector(uint32_t fcsr_bits)
141{
142 //Set FCSR invalid in "flag" field
143 int invalid_offset = Invalid + Flag_Field;
144 fcsr_bits = fcsr_bits | (1 << invalid_offset);
145
146 //Set FCSR invalid in "cause" flag
147 int cause_offset = Invalid + Cause_Field;
148 fcsr_bits = fcsr_bits | (1 << cause_offset);
149
150 return fcsr_bits;
151}
152
153bool
154isNan(void *val_ptr, int size)
155{
156 switch (size)
157 {
158 case 32:
159 {
160 uint32_t val_bits = *(uint32_t *) val_ptr;
161 return (bits(val_bits, 30, 23) == 0xFF);
162 }
163
164 case 64:
165 {
166 uint64_t val_bits = *(uint64_t *) val_ptr;
167 return (bits(val_bits, 62, 52) == 0x7FF);
168 }
169
170 default:
171 panic("Type unsupported. Size mismatch\n");
172 }
173}
174
175
176bool
177isQnan(void *val_ptr, int size)
178{
179 switch (size)
180 {
181 case 32:
182 {
183 uint32_t val_bits = *(uint32_t *) val_ptr;
184 return (bits(val_bits, 30, 22) == 0x1FE);
185 }
186
187 case 64:
188 {
189 uint64_t val_bits = *(uint64_t *) val_ptr;
190 return (bits(val_bits, 62, 51) == 0xFFE);
191 }
192
193 default:
194 panic("Type unsupported. Size mismatch\n");
195 }
196}
197
198bool
199isSnan(void *val_ptr, int size)
200{
201 switch (size)
202 {
203 case 32:
204 {
205 uint32_t val_bits = *(uint32_t *) val_ptr;
206 return (bits(val_bits, 30, 22) == 0x1FF);
207 }
208
209 case 64:
210 {
211 uint64_t val_bits = *(uint64_t *) val_ptr;
212 return (bits(val_bits, 62, 51) == 0xFFF);
213 }
214
215 default:
216 panic("Type unsupported. Size mismatch\n");
217 }
218}
219
220template <class CPU>
221void
222zeroRegisters(CPU *cpu)
223{
224 // Insure ISA semantics
225 // (no longer very clean due to the change in setIntReg() in the
226 // cpu model. Consider changing later.)
227 cpu->thread->setIntReg(ZeroReg, 0);
228 cpu->thread->setFloatReg(ZeroReg, 0.0);
229}
230
231void
232startupCPU(ThreadContext *tc, int cpuId)
233{
234 tc->activate(0/*tc->threadId()*/);
235}
236
237void
238initCPU(ThreadContext *tc, int cpuId)
239{}
240
241void
242copyRegs(ThreadContext *src, ThreadContext *dest)
243{
244 panic("Copy Regs Not Implemented Yet\n");
245}
246
247void
248copyMiscRegs(ThreadContext *src, ThreadContext *dest)
249{
250 panic("Copy Misc. Regs Not Implemented Yet\n");
251}
252void
253skipFunction(ThreadContext *tc)
254{
255 TheISA::PCState newPC = tc->pcState();
256 newPC.set(tc->readIntReg(ReturnAddressReg));
257 tc->pcState(newPC);
258}
259
260
261} // namespace MipsISA
|