1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#include "arch/mips/isa_traits.hh"
32#include "arch/mips/utility.hh"
33#include "config/full_system.hh"
34#include "cpu/thread_context.hh"
35#include "cpu/static_inst.hh"
36#include "sim/serialize.hh"
37#include "base/bitfield.hh"
38#include "base/misc.hh"
39
40#if FULL_SYSTEM
41#include "arch/mips/vtophys.hh"
42#include "mem/vport.hh"
43#endif
44
45
46using namespace MipsISA;
47using namespace std;
48
49namespace MipsISA {
50
51uint64_t
52getArgument(ThreadContext *tc, int number, bool fp)
53{
54#if FULL_SYSTEM
55 if (number < NumArgumentRegs) {
56 if (fp)
57 return tc->readFloatRegBits(ArgumentReg[number]);
58 else
59 return tc->readIntReg(ArgumentReg[number]);
60 } else {
61 Addr sp = tc->readIntReg(StackPointerReg);
| 1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#include "arch/mips/isa_traits.hh"
32#include "arch/mips/utility.hh"
33#include "config/full_system.hh"
34#include "cpu/thread_context.hh"
35#include "cpu/static_inst.hh"
36#include "sim/serialize.hh"
37#include "base/bitfield.hh"
38#include "base/misc.hh"
39
40#if FULL_SYSTEM
41#include "arch/mips/vtophys.hh"
42#include "mem/vport.hh"
43#endif
44
45
46using namespace MipsISA;
47using namespace std;
48
49namespace MipsISA {
50
51uint64_t
52getArgument(ThreadContext *tc, int number, bool fp)
53{
54#if FULL_SYSTEM
55 if (number < NumArgumentRegs) {
56 if (fp)
57 return tc->readFloatRegBits(ArgumentReg[number]);
58 else
59 return tc->readIntReg(ArgumentReg[number]);
60 } else {
61 Addr sp = tc->readIntReg(StackPointerReg);
|
63 uint64_t arg = vp->read<uint64_t>(sp +
64 (number-NumArgumentRegs) * sizeof(uint64_t));
65 tc->delVirtPort(vp);
66 return arg;
67 }
68#else
69 panic("getArgument() is Full system only\n");
70 M5_DUMMY_RETURN
71#endif
72}
73
74uint64_t
75fpConvert(ConvertType cvt_type, double fp_val)
76{
77
78 switch (cvt_type)
79 {
80 case SINGLE_TO_DOUBLE:
81 {
82 double sdouble_val = fp_val;
83 void *sdouble_ptr = &sdouble_val;
84 uint64_t sdp_bits = *(uint64_t *) sdouble_ptr;
85 return sdp_bits;
86 }
87
88 case SINGLE_TO_WORD:
89 {
90 int32_t sword_val = (int32_t) fp_val;
91 void *sword_ptr = &sword_val;
92 uint64_t sword_bits= *(uint32_t *) sword_ptr;
93 return sword_bits;
94 }
95
96 case WORD_TO_SINGLE:
97 {
98 float wfloat_val = fp_val;
99 void *wfloat_ptr = &wfloat_val;
100 uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr;
101 return wfloat_bits;
102 }
103
104 case WORD_TO_DOUBLE:
105 {
106 double wdouble_val = fp_val;
107 void *wdouble_ptr = &wdouble_val;
108 uint64_t wdp_bits = *(uint64_t *) wdouble_ptr;
109 return wdp_bits;
110 }
111
112 default:
113 panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type);
114 return 0;
115 }
116}
117
118double
119roundFP(double val, int digits)
120{
121 double digit_offset = pow(10.0,digits);
122 val = val * digit_offset;
123 val = val + 0.5;
124 val = floor(val);
125 val = val / digit_offset;
126 return val;
127}
128
129double
130truncFP(double val)
131{
132 int trunc_val = (int) val;
133 return (double) trunc_val;
134}
135
136bool
137getCondCode(uint32_t fcsr, int cc_idx)
138{
139 int shift = (cc_idx == 0) ? 23 : cc_idx + 24;
140 bool cc_val = (fcsr >> shift) & 0x00000001;
141 return cc_val;
142}
143
144uint32_t
145genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
146{
147 int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
148
149 fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 |
150 cc_val << cc_idx |
151 bits(fcsr, cc_idx - 1, 0);
152
153 return fcsr;
154}
155
156uint32_t
157genInvalidVector(uint32_t fcsr_bits)
158{
159 //Set FCSR invalid in "flag" field
160 int invalid_offset = Invalid + Flag_Field;
161 fcsr_bits = fcsr_bits | (1 << invalid_offset);
162
163 //Set FCSR invalid in "cause" flag
164 int cause_offset = Invalid + Cause_Field;
165 fcsr_bits = fcsr_bits | (1 << cause_offset);
166
167 return fcsr_bits;
168}
169
170bool
171isNan(void *val_ptr, int size)
172{
173 switch (size)
174 {
175 case 32:
176 {
177 uint32_t val_bits = *(uint32_t *) val_ptr;
178 return (bits(val_bits, 30, 23) == 0xFF);
179 }
180
181 case 64:
182 {
183 uint64_t val_bits = *(uint64_t *) val_ptr;
184 return (bits(val_bits, 62, 52) == 0x7FF);
185 }
186
187 default:
188 panic("Type unsupported. Size mismatch\n");
189 }
190}
191
192
193bool
194isQnan(void *val_ptr, int size)
195{
196 switch (size)
197 {
198 case 32:
199 {
200 uint32_t val_bits = *(uint32_t *) val_ptr;
201 return (bits(val_bits, 30, 22) == 0x1FE);
202 }
203
204 case 64:
205 {
206 uint64_t val_bits = *(uint64_t *) val_ptr;
207 return (bits(val_bits, 62, 51) == 0xFFE);
208 }
209
210 default:
211 panic("Type unsupported. Size mismatch\n");
212 }
213}
214
215bool
216isSnan(void *val_ptr, int size)
217{
218 switch (size)
219 {
220 case 32:
221 {
222 uint32_t val_bits = *(uint32_t *) val_ptr;
223 return (bits(val_bits, 30, 22) == 0x1FF);
224 }
225
226 case 64:
227 {
228 uint64_t val_bits = *(uint64_t *) val_ptr;
229 return (bits(val_bits, 62, 51) == 0xFFF);
230 }
231
232 default:
233 panic("Type unsupported. Size mismatch\n");
234 }
235}
236
237void
238copyRegs(ThreadContext *src, ThreadContext *dest)
239{
240 panic("Copy Regs Not Implemented Yet\n");
241}
242
243void
244copyMiscRegs(ThreadContext *src, ThreadContext *dest)
245{
246 panic("Copy Misc. Regs Not Implemented Yet\n");
247}
248
249template <class CPU>
250void
251zeroRegisters(CPU *cpu)
252{
253 // Insure ISA semantics
254 // (no longer very clean due to the change in setIntReg() in the
255 // cpu model. Consider changing later.)
256 cpu->thread->setIntReg(ZeroReg, 0);
257 cpu->thread->setFloatReg(ZeroReg, 0.0);
258}
259
260void
261startupCPU(ThreadContext *tc, int cpuId)
262{
263 tc->activate(0/*tc->getThreadNum()*/);
264}
265
266} // namespace MipsISA
| 63 uint64_t arg = vp->read<uint64_t>(sp +
64 (number-NumArgumentRegs) * sizeof(uint64_t));
65 tc->delVirtPort(vp);
66 return arg;
67 }
68#else
69 panic("getArgument() is Full system only\n");
70 M5_DUMMY_RETURN
71#endif
72}
73
74uint64_t
75fpConvert(ConvertType cvt_type, double fp_val)
76{
77
78 switch (cvt_type)
79 {
80 case SINGLE_TO_DOUBLE:
81 {
82 double sdouble_val = fp_val;
83 void *sdouble_ptr = &sdouble_val;
84 uint64_t sdp_bits = *(uint64_t *) sdouble_ptr;
85 return sdp_bits;
86 }
87
88 case SINGLE_TO_WORD:
89 {
90 int32_t sword_val = (int32_t) fp_val;
91 void *sword_ptr = &sword_val;
92 uint64_t sword_bits= *(uint32_t *) sword_ptr;
93 return sword_bits;
94 }
95
96 case WORD_TO_SINGLE:
97 {
98 float wfloat_val = fp_val;
99 void *wfloat_ptr = &wfloat_val;
100 uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr;
101 return wfloat_bits;
102 }
103
104 case WORD_TO_DOUBLE:
105 {
106 double wdouble_val = fp_val;
107 void *wdouble_ptr = &wdouble_val;
108 uint64_t wdp_bits = *(uint64_t *) wdouble_ptr;
109 return wdp_bits;
110 }
111
112 default:
113 panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type);
114 return 0;
115 }
116}
117
118double
119roundFP(double val, int digits)
120{
121 double digit_offset = pow(10.0,digits);
122 val = val * digit_offset;
123 val = val + 0.5;
124 val = floor(val);
125 val = val / digit_offset;
126 return val;
127}
128
129double
130truncFP(double val)
131{
132 int trunc_val = (int) val;
133 return (double) trunc_val;
134}
135
136bool
137getCondCode(uint32_t fcsr, int cc_idx)
138{
139 int shift = (cc_idx == 0) ? 23 : cc_idx + 24;
140 bool cc_val = (fcsr >> shift) & 0x00000001;
141 return cc_val;
142}
143
144uint32_t
145genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
146{
147 int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
148
149 fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 |
150 cc_val << cc_idx |
151 bits(fcsr, cc_idx - 1, 0);
152
153 return fcsr;
154}
155
156uint32_t
157genInvalidVector(uint32_t fcsr_bits)
158{
159 //Set FCSR invalid in "flag" field
160 int invalid_offset = Invalid + Flag_Field;
161 fcsr_bits = fcsr_bits | (1 << invalid_offset);
162
163 //Set FCSR invalid in "cause" flag
164 int cause_offset = Invalid + Cause_Field;
165 fcsr_bits = fcsr_bits | (1 << cause_offset);
166
167 return fcsr_bits;
168}
169
170bool
171isNan(void *val_ptr, int size)
172{
173 switch (size)
174 {
175 case 32:
176 {
177 uint32_t val_bits = *(uint32_t *) val_ptr;
178 return (bits(val_bits, 30, 23) == 0xFF);
179 }
180
181 case 64:
182 {
183 uint64_t val_bits = *(uint64_t *) val_ptr;
184 return (bits(val_bits, 62, 52) == 0x7FF);
185 }
186
187 default:
188 panic("Type unsupported. Size mismatch\n");
189 }
190}
191
192
193bool
194isQnan(void *val_ptr, int size)
195{
196 switch (size)
197 {
198 case 32:
199 {
200 uint32_t val_bits = *(uint32_t *) val_ptr;
201 return (bits(val_bits, 30, 22) == 0x1FE);
202 }
203
204 case 64:
205 {
206 uint64_t val_bits = *(uint64_t *) val_ptr;
207 return (bits(val_bits, 62, 51) == 0xFFE);
208 }
209
210 default:
211 panic("Type unsupported. Size mismatch\n");
212 }
213}
214
215bool
216isSnan(void *val_ptr, int size)
217{
218 switch (size)
219 {
220 case 32:
221 {
222 uint32_t val_bits = *(uint32_t *) val_ptr;
223 return (bits(val_bits, 30, 22) == 0x1FF);
224 }
225
226 case 64:
227 {
228 uint64_t val_bits = *(uint64_t *) val_ptr;
229 return (bits(val_bits, 62, 51) == 0xFFF);
230 }
231
232 default:
233 panic("Type unsupported. Size mismatch\n");
234 }
235}
236
237void
238copyRegs(ThreadContext *src, ThreadContext *dest)
239{
240 panic("Copy Regs Not Implemented Yet\n");
241}
242
243void
244copyMiscRegs(ThreadContext *src, ThreadContext *dest)
245{
246 panic("Copy Misc. Regs Not Implemented Yet\n");
247}
248
249template <class CPU>
250void
251zeroRegisters(CPU *cpu)
252{
253 // Insure ISA semantics
254 // (no longer very clean due to the change in setIntReg() in the
255 // cpu model. Consider changing later.)
256 cpu->thread->setIntReg(ZeroReg, 0);
257 cpu->thread->setFloatReg(ZeroReg, 0.0);
258}
259
260void
261startupCPU(ThreadContext *tc, int cpuId)
262{
263 tc->activate(0/*tc->getThreadNum()*/);
264}
265
266} // namespace MipsISA
|