1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#include "arch/mips/utility.hh"
32
33#include <cmath>
34
35#include "arch/mips/isa_traits.hh"
36#include "arch/mips/registers.hh"
37#include "arch/mips/vtophys.hh"
38#include "base/bitfield.hh"
| 1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#include "arch/mips/utility.hh"
32
33#include <cmath>
34
35#include "arch/mips/isa_traits.hh"
36#include "arch/mips/registers.hh"
37#include "arch/mips/vtophys.hh"
38#include "base/bitfield.hh"
|
40#include "cpu/static_inst.hh"
41#include "cpu/thread_context.hh"
42#include "mem/fs_translating_port_proxy.hh"
43#include "sim/serialize.hh"
44
45using namespace MipsISA;
46using namespace std;
47
48namespace MipsISA {
49
50uint64_t
51getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
52{
53 panic("getArgument() not implemented\n");
54 M5_DUMMY_RETURN
55}
56
57uint64_t
58fpConvert(ConvertType cvt_type, double fp_val)
59{
60
61 switch (cvt_type)
62 {
63 case SINGLE_TO_DOUBLE:
64 {
65 double sdouble_val = fp_val;
66 void *sdouble_ptr = &sdouble_val;
67 uint64_t sdp_bits = *(uint64_t *) sdouble_ptr;
68 return sdp_bits;
69 }
70
71 case SINGLE_TO_WORD:
72 {
73 int32_t sword_val = (int32_t) fp_val;
74 void *sword_ptr = &sword_val;
75 uint64_t sword_bits= *(uint32_t *) sword_ptr;
76 return sword_bits;
77 }
78
79 case WORD_TO_SINGLE:
80 {
81 float wfloat_val = fp_val;
82 void *wfloat_ptr = &wfloat_val;
83 uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr;
84 return wfloat_bits;
85 }
86
87 case WORD_TO_DOUBLE:
88 {
89 double wdouble_val = fp_val;
90 void *wdouble_ptr = &wdouble_val;
91 uint64_t wdp_bits = *(uint64_t *) wdouble_ptr;
92 return wdp_bits;
93 }
94
95 default:
96 panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type);
97 return 0;
98 }
99}
100
101double
102roundFP(double val, int digits)
103{
104 double digit_offset = pow(10.0,digits);
105 val = val * digit_offset;
106 val = val + 0.5;
107 val = floor(val);
108 val = val / digit_offset;
109 return val;
110}
111
112double
113truncFP(double val)
114{
115 int trunc_val = (int) val;
116 return (double) trunc_val;
117}
118
119bool
120getCondCode(uint32_t fcsr, int cc_idx)
121{
122 int shift = (cc_idx == 0) ? 23 : cc_idx + 24;
123 bool cc_val = (fcsr >> shift) & 0x00000001;
124 return cc_val;
125}
126
127uint32_t
128genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
129{
130 int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
131
132 fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
133 cc_val << cc_idx |
134 bits(fcsr, cc_idx - 1, 0);
135
136 return fcsr;
137}
138
139uint32_t
140genInvalidVector(uint32_t fcsr_bits)
141{
142 //Set FCSR invalid in "flag" field
143 int invalid_offset = Invalid + Flag_Field;
144 fcsr_bits = fcsr_bits | (1 << invalid_offset);
145
146 //Set FCSR invalid in "cause" flag
147 int cause_offset = Invalid + Cause_Field;
148 fcsr_bits = fcsr_bits | (1 << cause_offset);
149
150 return fcsr_bits;
151}
152
153bool
154isNan(void *val_ptr, int size)
155{
156 switch (size)
157 {
158 case 32:
159 {
160 uint32_t val_bits = *(uint32_t *) val_ptr;
161 return (bits(val_bits, 30, 23) == 0xFF);
162 }
163
164 case 64:
165 {
166 uint64_t val_bits = *(uint64_t *) val_ptr;
167 return (bits(val_bits, 62, 52) == 0x7FF);
168 }
169
170 default:
171 panic("Type unsupported. Size mismatch\n");
172 }
173}
174
175
176bool
177isQnan(void *val_ptr, int size)
178{
179 switch (size)
180 {
181 case 32:
182 {
183 uint32_t val_bits = *(uint32_t *) val_ptr;
184 return (bits(val_bits, 30, 22) == 0x1FE);
185 }
186
187 case 64:
188 {
189 uint64_t val_bits = *(uint64_t *) val_ptr;
190 return (bits(val_bits, 62, 51) == 0xFFE);
191 }
192
193 default:
194 panic("Type unsupported. Size mismatch\n");
195 }
196}
197
198bool
199isSnan(void *val_ptr, int size)
200{
201 switch (size)
202 {
203 case 32:
204 {
205 uint32_t val_bits = *(uint32_t *) val_ptr;
206 return (bits(val_bits, 30, 22) == 0x1FF);
207 }
208
209 case 64:
210 {
211 uint64_t val_bits = *(uint64_t *) val_ptr;
212 return (bits(val_bits, 62, 51) == 0xFFF);
213 }
214
215 default:
216 panic("Type unsupported. Size mismatch\n");
217 }
218}
219
220template <class CPU>
221void
222zeroRegisters(CPU *cpu)
223{
224 // Insure ISA semantics
225 // (no longer very clean due to the change in setIntReg() in the
226 // cpu model. Consider changing later.)
227 cpu->thread->setIntReg(ZeroReg, 0);
228 cpu->thread->setFloatReg(ZeroReg, 0.0);
229}
230
231void
232startupCPU(ThreadContext *tc, int cpuId)
233{
234 tc->activate();
235}
236
237void
238initCPU(ThreadContext *tc, int cpuId)
239{}
240
241void
242copyRegs(ThreadContext *src, ThreadContext *dest)
243{
244 // First loop through the integer registers.
245 for (int i = 0; i < NumIntRegs; i++)
246 dest->setIntRegFlat(i, src->readIntRegFlat(i));
247
248 // Then loop through the floating point registers.
249 for (int i = 0; i < NumFloatRegs; i++)
250 dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
251
252 // Would need to add condition-code regs if implemented
253 assert(NumCCRegs == 0);
254
255 // Copy misc. registers
256 for (int i = 0; i < NumMiscRegs; i++)
257 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
258
259 // Copy over the PC State
260 dest->pcState(src->pcState());
261}
262
263void
264copyMiscRegs(ThreadContext *src, ThreadContext *dest)
265{
266 panic("Copy Misc. Regs Not Implemented Yet\n");
267}
268void
269skipFunction(ThreadContext *tc)
270{
271 TheISA::PCState newPC = tc->pcState();
272 newPC.set(tc->readIntReg(ReturnAddressReg));
273 tc->pcState(newPC);
274}
275
276
277} // namespace MipsISA
| 40#include "cpu/static_inst.hh"
41#include "cpu/thread_context.hh"
42#include "mem/fs_translating_port_proxy.hh"
43#include "sim/serialize.hh"
44
45using namespace MipsISA;
46using namespace std;
47
48namespace MipsISA {
49
50uint64_t
51getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
52{
53 panic("getArgument() not implemented\n");
54 M5_DUMMY_RETURN
55}
56
57uint64_t
58fpConvert(ConvertType cvt_type, double fp_val)
59{
60
61 switch (cvt_type)
62 {
63 case SINGLE_TO_DOUBLE:
64 {
65 double sdouble_val = fp_val;
66 void *sdouble_ptr = &sdouble_val;
67 uint64_t sdp_bits = *(uint64_t *) sdouble_ptr;
68 return sdp_bits;
69 }
70
71 case SINGLE_TO_WORD:
72 {
73 int32_t sword_val = (int32_t) fp_val;
74 void *sword_ptr = &sword_val;
75 uint64_t sword_bits= *(uint32_t *) sword_ptr;
76 return sword_bits;
77 }
78
79 case WORD_TO_SINGLE:
80 {
81 float wfloat_val = fp_val;
82 void *wfloat_ptr = &wfloat_val;
83 uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr;
84 return wfloat_bits;
85 }
86
87 case WORD_TO_DOUBLE:
88 {
89 double wdouble_val = fp_val;
90 void *wdouble_ptr = &wdouble_val;
91 uint64_t wdp_bits = *(uint64_t *) wdouble_ptr;
92 return wdp_bits;
93 }
94
95 default:
96 panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type);
97 return 0;
98 }
99}
100
101double
102roundFP(double val, int digits)
103{
104 double digit_offset = pow(10.0,digits);
105 val = val * digit_offset;
106 val = val + 0.5;
107 val = floor(val);
108 val = val / digit_offset;
109 return val;
110}
111
112double
113truncFP(double val)
114{
115 int trunc_val = (int) val;
116 return (double) trunc_val;
117}
118
119bool
120getCondCode(uint32_t fcsr, int cc_idx)
121{
122 int shift = (cc_idx == 0) ? 23 : cc_idx + 24;
123 bool cc_val = (fcsr >> shift) & 0x00000001;
124 return cc_val;
125}
126
127uint32_t
128genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val)
129{
130 int cc_idx = (cc_num == 0) ? 23 : cc_num + 24;
131
132 fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
133 cc_val << cc_idx |
134 bits(fcsr, cc_idx - 1, 0);
135
136 return fcsr;
137}
138
139uint32_t
140genInvalidVector(uint32_t fcsr_bits)
141{
142 //Set FCSR invalid in "flag" field
143 int invalid_offset = Invalid + Flag_Field;
144 fcsr_bits = fcsr_bits | (1 << invalid_offset);
145
146 //Set FCSR invalid in "cause" flag
147 int cause_offset = Invalid + Cause_Field;
148 fcsr_bits = fcsr_bits | (1 << cause_offset);
149
150 return fcsr_bits;
151}
152
153bool
154isNan(void *val_ptr, int size)
155{
156 switch (size)
157 {
158 case 32:
159 {
160 uint32_t val_bits = *(uint32_t *) val_ptr;
161 return (bits(val_bits, 30, 23) == 0xFF);
162 }
163
164 case 64:
165 {
166 uint64_t val_bits = *(uint64_t *) val_ptr;
167 return (bits(val_bits, 62, 52) == 0x7FF);
168 }
169
170 default:
171 panic("Type unsupported. Size mismatch\n");
172 }
173}
174
175
176bool
177isQnan(void *val_ptr, int size)
178{
179 switch (size)
180 {
181 case 32:
182 {
183 uint32_t val_bits = *(uint32_t *) val_ptr;
184 return (bits(val_bits, 30, 22) == 0x1FE);
185 }
186
187 case 64:
188 {
189 uint64_t val_bits = *(uint64_t *) val_ptr;
190 return (bits(val_bits, 62, 51) == 0xFFE);
191 }
192
193 default:
194 panic("Type unsupported. Size mismatch\n");
195 }
196}
197
198bool
199isSnan(void *val_ptr, int size)
200{
201 switch (size)
202 {
203 case 32:
204 {
205 uint32_t val_bits = *(uint32_t *) val_ptr;
206 return (bits(val_bits, 30, 22) == 0x1FF);
207 }
208
209 case 64:
210 {
211 uint64_t val_bits = *(uint64_t *) val_ptr;
212 return (bits(val_bits, 62, 51) == 0xFFF);
213 }
214
215 default:
216 panic("Type unsupported. Size mismatch\n");
217 }
218}
219
220template <class CPU>
221void
222zeroRegisters(CPU *cpu)
223{
224 // Insure ISA semantics
225 // (no longer very clean due to the change in setIntReg() in the
226 // cpu model. Consider changing later.)
227 cpu->thread->setIntReg(ZeroReg, 0);
228 cpu->thread->setFloatReg(ZeroReg, 0.0);
229}
230
231void
232startupCPU(ThreadContext *tc, int cpuId)
233{
234 tc->activate();
235}
236
237void
238initCPU(ThreadContext *tc, int cpuId)
239{}
240
241void
242copyRegs(ThreadContext *src, ThreadContext *dest)
243{
244 // First loop through the integer registers.
245 for (int i = 0; i < NumIntRegs; i++)
246 dest->setIntRegFlat(i, src->readIntRegFlat(i));
247
248 // Then loop through the floating point registers.
249 for (int i = 0; i < NumFloatRegs; i++)
250 dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
251
252 // Would need to add condition-code regs if implemented
253 assert(NumCCRegs == 0);
254
255 // Copy misc. registers
256 for (int i = 0; i < NumMiscRegs; i++)
257 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
258
259 // Copy over the PC State
260 dest->pcState(src->pcState());
261}
262
263void
264copyMiscRegs(ThreadContext *src, ThreadContext *dest)
265{
266 panic("Copy Misc. Regs Not Implemented Yet\n");
267}
268void
269skipFunction(ThreadContext *tc)
270{
271 TheISA::PCState newPC = tc->pcState();
272 newPC.set(tc->readIntReg(ReturnAddressReg));
273 tc->pcState(newPC);
274}
275
276
277} // namespace MipsISA
|