1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34#include "arch/mips/utility.hh"
35#include "base/bitfield.hh"
36#include "base/misc.hh"
37#include "config/full_system.hh"
38#include "cpu/static_inst.hh"
39#include "cpu/thread_context.hh"
40#include "sim/serialize.hh"
41
42#include "arch/mips/registers.hh"
43#include "arch/mips/vtophys.hh"
44#include "mem/vport.hh"
45
46
47using namespace MipsISA;
48using namespace std;
49
50namespace MipsISA {
51
52uint64_t
53getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
54{
55 panic("getArgument() not implemented\n");
56 M5_DUMMY_RETURN
57}
58
59uint64_t
60fpConvert(ConvertType cvt_type, double fp_val)
61{
62
63 switch (cvt_type)
64 {

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232
233void
234startupCPU(ThreadContext *tc, int cpuId)
235{
236 tc->activate(0/*tc->threadId()*/);
237}
238
239void
240initCPU(ThreadContext *tc, int cpuId)
241{}
242
243void
244copyRegs(ThreadContext *src, ThreadContext *dest)
245{
246 panic("Copy Regs Not Implemented Yet\n");
247}
248
249void
250copyMiscRegs(ThreadContext *src, ThreadContext *dest)
251{

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