1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#ifndef __ARCH_MIPS_TYPES_HH__
32#define __ARCH_MIPS_TYPES_HH__
33
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35
36namespace MipsISA
37{
38 typedef uint32_t MachInst;
39 typedef uint64_t ExtMachInst;
40 typedef uint16_t RegIndex;
41
42 typedef uint32_t IntReg;
43 typedef uint64_t LargestRead;
44
45
46 // floating point register file entry type
47 typedef uint32_t FloatReg32;
48 typedef uint64_t FloatReg64;
49 typedef uint64_t FloatRegBits;
50
51 typedef double FloatRegVal;
52 typedef double FloatReg;
53
54 // cop-0/cop-1 system control register
55 typedef uint64_t MiscReg;
56
57 typedef union {
58 IntReg intreg;
59 FloatReg fpreg;
60 MiscReg ctrlreg;
61 } AnyReg;
62
63 //used in FP convert & round function
64 enum ConvertType{
65 SINGLE_TO_DOUBLE,
66 SINGLE_TO_WORD,
67 SINGLE_TO_LONG,
68
69 DOUBLE_TO_SINGLE,
70 DOUBLE_TO_WORD,
71 DOUBLE_TO_LONG,
72
73 LONG_TO_SINGLE,
74 LONG_TO_DOUBLE,
75 LONG_TO_WORD,
76 LONG_TO_PS,
77
78 WORD_TO_SINGLE,
79 WORD_TO_DOUBLE,
80 WORD_TO_LONG,
81 WORD_TO_PS,
82
83 PL_TO_SINGLE,
84 PU_TO_SINGLE
85 };
86
87 //used in FP convert & round function
88 enum RoundMode{
89 RND_ZERO,
90 RND_DOWN,
91 RND_UP,
92 RND_NEAREST
93 };
94
95struct CoreSpecific {
96 /* Note: It looks like it will be better to allow simulator users
97 to specify the values of individual variables instead of requiring
98 users to define the values of entire registers
99 Especially since a lot of these variables can be created from other
100 user parameters (cache descriptions)
101 -jpp
102 */
103 // MIPS CP0 State - First individual variables
104 // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM, Volume III (PRA)
105 unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt
106 unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt
107 unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set
108 unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options
109 unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS)
110 unsigned CP0_PRId_ProcessorID; // Page 105
111 unsigned CP0_PRId_Revision; // Page 105
112 unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor system
113 unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode
114 unsigned CP0_Config_AT; //Page 109
115 unsigned CP0_Config_AR; //Page 109
116 unsigned CP0_Config_MT; //Page 109
117 unsigned CP0_Config_VI; //Page 109
118 unsigned CP0_Config1_M; // Page 110
119 unsigned CP0_Config1_MMU; // Page 110
120 unsigned CP0_Config1_IS; // Page 110
121 unsigned CP0_Config1_IL; // Page 111
122 unsigned CP0_Config1_IA; // Page 111
123 unsigned CP0_Config1_DS; // Page 111
124 unsigned CP0_Config1_DL; // Page 112
125 unsigned CP0_Config1_DA; // Page 112
126 bool CP0_Config1_C2; // Page 112
127 bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32
128 bool CP0_Config1_PC;// Page 112
129 bool CP0_Config1_WR;// Page 113
130 bool CP0_Config1_CA;// Page 113
131 bool CP0_Config1_EP;// Page 113
132 bool CP0_Config1_FP;// Page 113
133 bool CP0_Config2_M; // Page 114
134 unsigned CP0_Config2_TU;// Page 114
135 unsigned CP0_Config2_TS;// Page 114
136 unsigned CP0_Config2_TL;// Page 115
137 unsigned CP0_Config2_TA;// Page 115
138 unsigned CP0_Config2_SU;// Page 115
139 unsigned CP0_Config2_SS;// Page 115
140 unsigned CP0_Config2_SL;// Page 116
141 unsigned CP0_Config2_SA;// Page 116
142 bool CP0_Config3_M; //// Page 117
143 bool CP0_Config3_DSPP;// Page 117
144 bool CP0_Config3_LPA;// Page 117
145 bool CP0_Config3_VEIC;// Page 118
146 bool CP0_Config3_VInt; // Page 118
147 bool CP0_Config3_SP;// Page 118
148 bool CP0_Config3_MT;// Page 119
149 bool CP0_Config3_SM;// Page 119
150 bool CP0_Config3_TL;// Page 119
151
152 bool CP0_WatchHi_M; // Page 124
153 bool CP0_PerfCtr_M; // Page 130
154 bool CP0_PerfCtr_W; // Page 130
155
156
157 // Then, whole registers
158 unsigned CP0_PRId;
159 unsigned CP0_Config;
160 unsigned CP0_Config1;
161 unsigned CP0_Config2;
162 unsigned CP0_Config3;
163};
164
165} // namespace MipsISA
166
167#endif
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