types.hh (5222:bb733a878f85) | types.hh (5251:8de83cada19d) |
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1/* | 1/* |
2 * Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved | 2 * Copyright (c) 2007 MIPS Technologies, Inc. 3 * All rights reserved. |
3 * | 4 * |
4 * This software is part of the M5 simulator. | 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. |
5 * | 15 * |
6 * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 7 * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 8 * TO THESE TERMS AND CONDITIONS. | 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
9 * | 27 * |
10 * Permission is granted to use, copy, create derivative works and 11 * distribute this software and such derivative works for any purpose, 12 * so long as (1) the copyright notice above, this grant of permission, 13 * and the disclaimer below appear in all copies and derivative works 14 * made, (2) the copyright notice above is augmented as appropriate to 15 * reflect the addition of any new copyrightable work in a derivative 16 * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3) 17 * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any 18 * advertising or publicity pertaining to the use or distribution of 19 * this software without specific, written prior authorization. 20 * 21 * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND 22 * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 23 * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 25 * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 26 * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 27 * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 28 * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 29 * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 30 * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 31 * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 32 * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 33 * 34 * Authors: Korey L. Sewell | 28 * Authors: Korey Sewell |
35 */ 36 37#ifndef __ARCH_MIPS_TYPES_HH__ 38#define __ARCH_MIPS_TYPES_HH__ 39 40#include "sim/host.hh" 41 42namespace MipsISA --- 53 unchanged lines hidden (view full) --- 96 //used in FP convert & round function 97 enum RoundMode{ 98 RND_ZERO, 99 RND_DOWN, 100 RND_UP, 101 RND_NEAREST 102 }; 103 | 29 */ 30 31#ifndef __ARCH_MIPS_TYPES_HH__ 32#define __ARCH_MIPS_TYPES_HH__ 33 34#include "sim/host.hh" 35 36namespace MipsISA --- 53 unchanged lines hidden (view full) --- 90 //used in FP convert & round function 91 enum RoundMode{ 92 RND_ZERO, 93 RND_DOWN, 94 RND_UP, 95 RND_NEAREST 96 }; 97 |
98struct CoreSpecific { 99 /* Note: It looks like it will be better to allow simulator users 100 to specify the values of individual variables instead of requiring 101 users to define the values of entire registers 102 Especially since a lot of these variables can be created from other 103 user parameters (cache descriptions) 104 -jpp 105 */ 106 // MIPS CP0 State - First individual variables 107 // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM, Volume III (PRA) 108 unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt 109 unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt 110 unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set 111 unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options 112 unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS) 113 unsigned CP0_PRId_ProcessorID; // Page 105 114 unsigned CP0_PRId_Revision; // Page 105 115 unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor system 116 unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode 117 unsigned CP0_Config_AT; //Page 109 118 unsigned CP0_Config_AR; //Page 109 119 unsigned CP0_Config_MT; //Page 109 120 unsigned CP0_Config_VI; //Page 109 121 unsigned CP0_Config1_M; // Page 110 122 unsigned CP0_Config1_MMU; // Page 110 123 unsigned CP0_Config1_IS; // Page 110 124 unsigned CP0_Config1_IL; // Page 111 125 unsigned CP0_Config1_IA; // Page 111 126 unsigned CP0_Config1_DS; // Page 111 127 unsigned CP0_Config1_DL; // Page 112 128 unsigned CP0_Config1_DA; // Page 112 129 bool CP0_Config1_C2; // Page 112 130 bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32 131 bool CP0_Config1_PC;// Page 112 132 bool CP0_Config1_WR;// Page 113 133 bool CP0_Config1_CA;// Page 113 134 bool CP0_Config1_EP;// Page 113 135 bool CP0_Config1_FP;// Page 113 136 bool CP0_Config2_M; // Page 114 137 unsigned CP0_Config2_TU;// Page 114 138 unsigned CP0_Config2_TS;// Page 114 139 unsigned CP0_Config2_TL;// Page 115 140 unsigned CP0_Config2_TA;// Page 115 141 unsigned CP0_Config2_SU;// Page 115 142 unsigned CP0_Config2_SS;// Page 115 143 unsigned CP0_Config2_SL;// Page 116 144 unsigned CP0_Config2_SA;// Page 116 145 bool CP0_Config3_M; //// Page 117 146 bool CP0_Config3_DSPP;// Page 117 147 bool CP0_Config3_LPA;// Page 117 148 bool CP0_Config3_VEIC;// Page 118 149 bool CP0_Config3_VInt; // Page 118 150 bool CP0_Config3_SP;// Page 118 151 bool CP0_Config3_MT;// Page 119 152 bool CP0_Config3_SM;// Page 119 153 bool CP0_Config3_TL;// Page 119 154 155 bool CP0_WatchHi_M; // Page 124 156 bool CP0_PerfCtr_M; // Page 130 157 bool CP0_PerfCtr_W; // Page 130 158 159 160 // Then, whole registers 161 unsigned CP0_PRId; 162 unsigned CP0_Config; 163 unsigned CP0_Config1; 164 unsigned CP0_Config2; 165 unsigned CP0_Config3; 166}; 167 |
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104} // namespace MipsISA 105 106#endif | 168} // namespace MipsISA 169 170#endif |