1/*
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#ifndef __ARCH_MIPS_TYPES_HH__
32#define __ARCH_MIPS_TYPES_HH__
33
34#include "base/types.hh"
35
36namespace MipsISA
37{
38
39typedef uint32_t MachInst;
40typedef uint64_t ExtMachInst;
41
42typedef uint64_t LargestRead;
43
44//used in FP convert & round function
45enum ConvertType{
46 SINGLE_TO_DOUBLE,
47 SINGLE_TO_WORD,
48 SINGLE_TO_LONG,
49
50 DOUBLE_TO_SINGLE,
51 DOUBLE_TO_WORD,
52 DOUBLE_TO_LONG,
53
54 LONG_TO_SINGLE,
55 LONG_TO_DOUBLE,
56 LONG_TO_WORD,
57 LONG_TO_PS,
58
59 WORD_TO_SINGLE,
60 WORD_TO_DOUBLE,
61 WORD_TO_LONG,
62 WORD_TO_PS,
63
64 PL_TO_SINGLE,
65 PU_TO_SINGLE
66};
67
68//used in FP convert & round function
69enum RoundMode{
70 RND_ZERO,
71 RND_DOWN,
72 RND_UP,
73 RND_NEAREST
74};
75
76struct CoreSpecific {
77 /* Note: It looks like it will be better to allow simulator users
78 to specify the values of individual variables instead of requiring
79 users to define the values of entire registers
80 Especially since a lot of these variables can be created from other
81 user parameters (cache descriptions)
82 -jpp
83 */
84 // MIPS CP0 State - First individual variables
85 // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM,
86 // Volume III (PRA)
87 unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt
88 unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt
89 unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set
90 unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options
91 unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS)
92 unsigned CP0_PRId_ProcessorID; // Page 105
93 unsigned CP0_PRId_Revision; // Page 105
94 unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor
95 //system
96 unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode
97 unsigned CP0_Config_AT; //Page 109
98 unsigned CP0_Config_AR; //Page 109
99 unsigned CP0_Config_MT; //Page 109
100 unsigned CP0_Config_VI; //Page 109
101 unsigned CP0_Config1_M; // Page 110
102 unsigned CP0_Config1_MMU; // Page 110
103 unsigned CP0_Config1_IS; // Page 110
104 unsigned CP0_Config1_IL; // Page 111
105 unsigned CP0_Config1_IA; // Page 111
106 unsigned CP0_Config1_DS; // Page 111
107 unsigned CP0_Config1_DL; // Page 112
108 unsigned CP0_Config1_DA; // Page 112
109 bool CP0_Config1_C2; // Page 112
110 bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32
111 bool CP0_Config1_PC;// Page 112
112 bool CP0_Config1_WR;// Page 113
113 bool CP0_Config1_CA;// Page 113
114 bool CP0_Config1_EP;// Page 113
115 bool CP0_Config1_FP;// Page 113
116 bool CP0_Config2_M; // Page 114
117 unsigned CP0_Config2_TU;// Page 114
118 unsigned CP0_Config2_TS;// Page 114
119 unsigned CP0_Config2_TL;// Page 115
120 unsigned CP0_Config2_TA;// Page 115
121 unsigned CP0_Config2_SU;// Page 115
122 unsigned CP0_Config2_SS;// Page 115
123 unsigned CP0_Config2_SL;// Page 116
124 unsigned CP0_Config2_SA;// Page 116
125 bool CP0_Config3_M; //// Page 117
126 bool CP0_Config3_DSPP;// Page 117
127 bool CP0_Config3_LPA;// Page 117
128 bool CP0_Config3_VEIC;// Page 118
129 bool CP0_Config3_VInt; // Page 118
130 bool CP0_Config3_SP;// Page 118
131 bool CP0_Config3_MT;// Page 119
132 bool CP0_Config3_SM;// Page 119
133 bool CP0_Config3_TL;// Page 119
134
135 bool CP0_WatchHi_M; // Page 124
136 bool CP0_PerfCtr_M; // Page 130
137 bool CP0_PerfCtr_W; // Page 130
138
139
140 // Then, whole registers
141 unsigned CP0_PRId;
142 unsigned CP0_Config;
143 unsigned CP0_Config1;
144 unsigned CP0_Config2;
145 unsigned CP0_Config3;
146};
147
148} // namespace MipsISA
149
150#endif
2 * Copyright (c) 2007 MIPS Technologies, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Korey Sewell
29 */
30
31#ifndef __ARCH_MIPS_TYPES_HH__
32#define __ARCH_MIPS_TYPES_HH__
33
34#include "base/types.hh"
35
36namespace MipsISA
37{
38
39typedef uint32_t MachInst;
40typedef uint64_t ExtMachInst;
41
42typedef uint64_t LargestRead;
43
44//used in FP convert & round function
45enum ConvertType{
46 SINGLE_TO_DOUBLE,
47 SINGLE_TO_WORD,
48 SINGLE_TO_LONG,
49
50 DOUBLE_TO_SINGLE,
51 DOUBLE_TO_WORD,
52 DOUBLE_TO_LONG,
53
54 LONG_TO_SINGLE,
55 LONG_TO_DOUBLE,
56 LONG_TO_WORD,
57 LONG_TO_PS,
58
59 WORD_TO_SINGLE,
60 WORD_TO_DOUBLE,
61 WORD_TO_LONG,
62 WORD_TO_PS,
63
64 PL_TO_SINGLE,
65 PU_TO_SINGLE
66};
67
68//used in FP convert & round function
69enum RoundMode{
70 RND_ZERO,
71 RND_DOWN,
72 RND_UP,
73 RND_NEAREST
74};
75
76struct CoreSpecific {
77 /* Note: It looks like it will be better to allow simulator users
78 to specify the values of individual variables instead of requiring
79 users to define the values of entire registers
80 Especially since a lot of these variables can be created from other
81 user parameters (cache descriptions)
82 -jpp
83 */
84 // MIPS CP0 State - First individual variables
85 // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM,
86 // Volume III (PRA)
87 unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt
88 unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt
89 unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set
90 unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options
91 unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS)
92 unsigned CP0_PRId_ProcessorID; // Page 105
93 unsigned CP0_PRId_Revision; // Page 105
94 unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor
95 //system
96 unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode
97 unsigned CP0_Config_AT; //Page 109
98 unsigned CP0_Config_AR; //Page 109
99 unsigned CP0_Config_MT; //Page 109
100 unsigned CP0_Config_VI; //Page 109
101 unsigned CP0_Config1_M; // Page 110
102 unsigned CP0_Config1_MMU; // Page 110
103 unsigned CP0_Config1_IS; // Page 110
104 unsigned CP0_Config1_IL; // Page 111
105 unsigned CP0_Config1_IA; // Page 111
106 unsigned CP0_Config1_DS; // Page 111
107 unsigned CP0_Config1_DL; // Page 112
108 unsigned CP0_Config1_DA; // Page 112
109 bool CP0_Config1_C2; // Page 112
110 bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32
111 bool CP0_Config1_PC;// Page 112
112 bool CP0_Config1_WR;// Page 113
113 bool CP0_Config1_CA;// Page 113
114 bool CP0_Config1_EP;// Page 113
115 bool CP0_Config1_FP;// Page 113
116 bool CP0_Config2_M; // Page 114
117 unsigned CP0_Config2_TU;// Page 114
118 unsigned CP0_Config2_TS;// Page 114
119 unsigned CP0_Config2_TL;// Page 115
120 unsigned CP0_Config2_TA;// Page 115
121 unsigned CP0_Config2_SU;// Page 115
122 unsigned CP0_Config2_SS;// Page 115
123 unsigned CP0_Config2_SL;// Page 116
124 unsigned CP0_Config2_SA;// Page 116
125 bool CP0_Config3_M; //// Page 117
126 bool CP0_Config3_DSPP;// Page 117
127 bool CP0_Config3_LPA;// Page 117
128 bool CP0_Config3_VEIC;// Page 118
129 bool CP0_Config3_VInt; // Page 118
130 bool CP0_Config3_SP;// Page 118
131 bool CP0_Config3_MT;// Page 119
132 bool CP0_Config3_SM;// Page 119
133 bool CP0_Config3_TL;// Page 119
134
135 bool CP0_WatchHi_M; // Page 124
136 bool CP0_PerfCtr_M; // Page 130
137 bool CP0_PerfCtr_W; // Page 130
138
139
140 // Then, whole registers
141 unsigned CP0_PRId;
142 unsigned CP0_Config;
143 unsigned CP0_Config1;
144 unsigned CP0_Config2;
145 unsigned CP0_Config3;
146};
147
148} // namespace MipsISA
149
150#endif