tlb.cc (8607:5fb918115c07) tlb.cc (8696:642f83fafffb)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Nathan Binkert
30 * Steve Reinhardt
31 * Jaidev Patwardhan
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Nathan Binkert
30 * Steve Reinhardt
31 * Jaidev Patwardhan
32 * Zhengxing Li
33 * Deyuan Guo
32 */
33
34#include <string>
35#include <vector>
36
37#include "arch/mips/faults.hh"
38#include "arch/mips/pagetable.hh"
39#include "arch/mips/pra_constants.hh"

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345 EvenOdd = 0;
346 } else {
347 // Check odd bits
348 Valid = pte->V1;
349 EvenOdd = 1;
350 }
351
352 if (Valid == false) {
34 */
35
36#include <string>
37#include <vector>
38
39#include "arch/mips/faults.hh"
40#include "arch/mips/pagetable.hh"
41#include "arch/mips/pra_constants.hh"

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347 EvenOdd = 0;
348 } else {
349 // Check odd bits
350 Valid = pte->V1;
351 EvenOdd = 1;
352 }
353
354 if (Valid == false) {
353 return new InvalidFault(Asid, vaddr, vpn, false);
355 return new TlbInvalidFault(Asid, vaddr, VPN, false);
354 } else {
355 // Ok, this is really a match, set paddr
356 Addr PAddr;
357 if (EvenOdd == 0) {
358 PAddr = pte->PFN0;
359 } else {
360 PAddr = pte->PFN1;
361 }
362 PAddr >>= (pte->AddrShiftAmount - 12);
363 PAddr <<= pte->AddrShiftAmount;
364 PAddr |= (vaddr & pte->OffsetMask);
365 req->setPaddr(PAddr);
366 }
367 } else {
368 // Didn't find any match, return a TLB Refill Exception
356 } else {
357 // Ok, this is really a match, set paddr
358 Addr PAddr;
359 if (EvenOdd == 0) {
360 PAddr = pte->PFN0;
361 } else {
362 PAddr = pte->PFN1;
363 }
364 PAddr >>= (pte->AddrShiftAmount - 12);
365 PAddr <<= pte->AddrShiftAmount;
366 PAddr |= (vaddr & pte->OffsetMask);
367 req->setPaddr(PAddr);
368 }
369 } else {
370 // Didn't find any match, return a TLB Refill Exception
369 return new RefillFault(Asid, vaddr, vpn, false);
371 return new TlbRefillFault(Asid, vaddr, VPN, false);
370 }
371 }
372 return checkCacheability(req);
373#endif
374}
375
376Fault
377TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)

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440 } else {
441 // Check odd bits
442 Valid = pte->V1;
443 Dirty = pte->D1;
444 EvenOdd = 1;
445 }
446
447 if (Valid == false) {
372 }
373 }
374 return checkCacheability(req);
375#endif
376}
377
378Fault
379TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)

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442 } else {
443 // Check odd bits
444 Valid = pte->V1;
445 Dirty = pte->D1;
446 EvenOdd = 1;
447 }
448
449 if (Valid == false) {
448 return new InvalidFault(Asid, vaddr, VPN, true);
450 return new TlbInvalidFault(Asid, vaddr, VPN, write);
449 } else {
450 // Ok, this is really a match, set paddr
451 } else {
452 // Ok, this is really a match, set paddr
451 if (!Dirty) {
453 if (!Dirty && write) {
452 return new TlbModifiedFault(Asid, vaddr, VPN);
453 }
454 Addr PAddr;
455 if (EvenOdd == 0) {
456 PAddr = pte->PFN0;
457 } else {
458 PAddr = pte->PFN1;
459 }
460 PAddr >>= (pte->AddrShiftAmount - 12);
461 PAddr <<= pte->AddrShiftAmount;
462 PAddr |= (vaddr & pte->OffsetMask);
463 req->setPaddr(PAddr);
464 }
465 } else {
466 // Didn't find any match, return a TLB Refill Exception
454 return new TlbModifiedFault(Asid, vaddr, VPN);
455 }
456 Addr PAddr;
457 if (EvenOdd == 0) {
458 PAddr = pte->PFN0;
459 } else {
460 PAddr = pte->PFN1;
461 }
462 PAddr >>= (pte->AddrShiftAmount - 12);
463 PAddr <<= pte->AddrShiftAmount;
464 PAddr |= (vaddr & pte->OffsetMask);
465 req->setPaddr(PAddr);
466 }
467 } else {
468 // Didn't find any match, return a TLB Refill Exception
467 return new RefillFault(Asid, vaddr, VPN, true);
469 return new TlbRefillFault(Asid, vaddr, VPN, write);
468 }
469 }
470 return checkCacheability(req);
471#endif
472}
473
474Fault
475TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)

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471 }
472 return checkCacheability(req);
473#endif
474}
475
476Fault
477TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)

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